Summary:
- This commit fixes DEBUGASSERT in lm3s_ethernet.c
Impact:
- lm3s_ethernet.c only
Testing:
- Tested with lm3s6965-ek:discover with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes a compile warning in cxd56_sdhci.c
Impact:
- None
Testing:
- Built with spresense:wifi
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit replaces SHES related headers under cxd56xx
Impact:
- No impact
Testing:
- Build check only
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds imx_enet driver derived from imxrt_enet
Impact:
- imx6 only
Testing:
- Tested with sabre-6quad:netnsh
- NOTE: telnetd works with QEMU
Summary:
- This commit fixes peripheral IP offsets in AIPS-2
Impact:
- No impact because there is no drivers
Testing:
- Tested with sabre-6quad:nsh and sabre-6quad:smp
Summary:
- During repeating ostest with sabre-6quad:smp (QEMU),
I noticed that pthread_rwlock_test sometimes stops
- Finally, I found that nxtask_exit() released a critical
section too early before context switching which resulted in
selecting inappropriate TCB
- This commit fixes this issue by moving nxsched_resume_scheduler()
from nxtask_exit() to up_exit() and also removing
spin_setbit() and spin_clrbit() from nxtask_exit()
because the caller holds a critical section
- To be consistent with non-SMP cases, the above changes
were done for all CPU architectures
Impact:
- This commit affects all CPU architectures regardless of SMP
Testing:
- Tested with ostest with the following configs
- sabre-6quad:smp (QEMU, dev board), sabre-6quad:nsh (QEMU)
- spresense:wifi_smp
- sim:smp, sim:ostest
- maix-bit:smp (QEMU)
- esp32-devkitc:smp (QEMU)
- lc823450-xgevk:rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
When the architectural support for STM32G4 family was added, the
reference manual (RM0440) was at revision 2. Since then, it has
undergone several revisions. One significant change is in the
table of FLASH wait states: section 3.3.3 table 9. The outcome
of this change is that fewer FLASH wait states are needed for
most CPU clock (HCLK) frequencies. Notably, if running the CPU
clock at the maximum 170 MHz, only 4 FLASH wait states are
needed, rather than the previously programmed 8 wait states.
This gives a noticeable performance boost.
arch/arm/src/stm32/stm32g4xxxx_rcc.c:
* FLASH_ACR_LATENCY_SETTING: Reimplement compile-time logic
that selects the required wait state setting to use the new
updated table.
* Update all comments to indicate that RM0440 Rev 5 is used.
* Update section numbers mentioned in comments in cases where
they have changed due to added sections in the manual.
