Commit Graph

19495 Commits

Author SHA1 Message Date
Jiuzhu Dong
3a70962b7a fs/directory: use file mode to manage directory
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-08-09 23:30:01 +08:00
Jiuzhu Dong
094e986bbd fcntl/O_CLOEXEC: add O_CLOEXEC map for hostfs
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-08-09 23:30:01 +08:00
Ville Juven
31bb362aab risc-v: Fix kernel MMU mapping for L3 table
The L3 table address was calculated incorrectly. For every 2MiB of
mapped memory, an offset of 4KiB is needed from the base of the L3
table. The old calculation failed if paddr was not aligned to a 2MiB
boundary.
2022-08-09 23:14:46 +08:00
David Sidrane
2e7b594bf4 s32k1xx:Add s32k146 DMAMUX 2022-08-09 16:29:21 +03:00
David Sidrane
3813320c31 s32k1xx_edma:Add Looping and cleanup
s32k1xx:EDMA Use aligned_data macros

s32k1xx:EDMA CONFIG_ARCH_CHIP_S32K14x->CONFIG_ARCH_CHIP_S32K14X

s32k1xx:EDMA remove FAR keyword

s32k1xx:EDMA Fix C&P error from Kinetis

s32k1xx:EDMA TCD Alignment of 32 Bytes to support Scatter/Gather

s32k1xx:EDMA Fix access violation

s32k1xx:dmamux fixed missing closing paren
2022-08-09 16:29:21 +03:00
raiden00pl
a05db5299e arch/arm/src/stm32f7: port PWM driver from arch/stm32
This change adds support for the following features:
  1. PWM complementary outputs
  2. interface for low-level PWM operations
  3. support for all PWM channel modes
  4. support for internal PWM channels (TIM1/TIM8)
  5. support for PWM channel polarity and IDLE state
  6. support for TRGO and BREAK
2022-08-09 12:37:49 +08:00
raiden00pl
fd02855c63 arch/stm32f7: rename PWM complementary output pins from CHxN to CHxNOUT (always output) 2022-08-09 12:37:49 +08:00
David Sidrane
050ce3e0d3 kinetis:spi remove ttype & do cache ops 2022-08-09 10:46:31 +08:00
David Sidrane
22580584d2 kinetis:[lp]serial remove ttype & do cache ops 2022-08-09 10:46:31 +08:00
David Sidrane
7a7a01153b Kinetis:edma Cleanup
Kientis:edma Cleanup

    Kinetis:EDMA Interrupt on last TCD

    Kintis:edma remove dcache operations on passed data

       Data can be chained in TCD and both read and write
       can be in the chain. So the dmach ttype is not
       relevent for all; the TCDs. Therefor we only perform
       dcache operations on internal strutures, The caller
       must perform dcache operations on their data.

kinetis:EDMA TCD Alignment of 32 Bytes to support Scatter/Gather
2022-08-09 10:46:31 +08:00
Nathan Hartman
dd718e78f7 Fix typos 2022-08-07 23:33:19 +08:00
p-eaglelaw
631ae0032e fix warning 2022-08-07 13:03:39 +08:00
p-eaglelaw
702e2f3680 remove unused lib,fix according review comments 2022-08-07 01:57:02 +08:00
David Sidrane
55aaba53fc imxrt:SPI add DMA support 2022-08-06 15:32:07 +08:00
David Sidrane
fa58381e58 imxrt:serial add TX & RX DMA support
imxrt:serial ioctl should call to proper setup
2022-08-06 15:32:07 +08:00
David Sidrane
85ec2e1446 imxrt:Add LPI2C DMA 2022-08-06 15:32:07 +08:00
David Sidrane
f34acdb936 imxrt:lpi2c add parens for macros expansions 2022-08-06 15:32:07 +08:00
Peter van der Perk
22d41f6b9c LPC17xx_40xx PWM multichannel support
USB no softconnect
SocketCAN kconfig fixes
2022-08-06 15:31:38 +08:00
David Sidrane
6ab76bfc7c imrt105x:ENET Match Data sheet Naming 2022-08-06 15:31:23 +08:00
David Sidrane
b9a6b01e6c imrt102x:ENET Match Data sheet Naming 2022-08-06 15:31:23 +08:00
David Sidrane
0628019c2c imxrt:Enet ensure proper dcache for Writeback mode
Use aligned_data
   added proper handeling for Writeback
2022-08-06 15:31:23 +08:00
David Sidrane
522a949ed5 imxrt:enet Better interrupt state handeling 2022-08-06 15:31:23 +08:00
David Sidrane
1d88f8df37 imxrt:pinmux ENET2 correct ALT for GPIO_ENET2_REF_CLK2 2022-08-06 15:31:23 +08:00
David Sidrane
bced1a3cb4 imxrt:Fix Ethernet Clocking 2022-08-06 15:31:23 +08:00
David Sidrane
6a2c1fb1de imxrt:Kconfig add IMXRT_PHY_POLLING 2022-08-06 15:31:23 +08:00
David Sidrane
81f03a9151 imxrt:ETH Add Support for ETH2 2022-08-06 15:31:23 +08:00
David Sidrane
49d304257c imxrt:All boards ARCH_PHY_INTERRUPT is a board property 2022-08-06 15:31:23 +08:00
David Sidrane
3af910f8b6 imxrt:Ethernet Add LAN8742A support 2022-08-06 15:31:23 +08:00
Petro Karashchenko
b3cd9090d1 drivers/net: make sure that net driver d_buf is 16-bit aligned
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-08-05 22:21:37 +08:00
raiden00pl
93584f8668 arch/stm32f0l0g0: add SPI3 support (STM32G0B0 chips) 2022-08-05 13:57:56 +08:00
Xiang Xiao
c61381da56 arch/risc-v: Fix error: invalid application of 'sizeof' to incomplete type 'struct tls_info_s'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-05 08:45:11 +03:00
David Sidrane
33efeeeafd imxrt:EDMA add loop support
imxrt:edma imxrt_dmach_{xfrsetup|getcount} DMACH_HANDLE *->DMACH_HANDLE

imxrt:EDMA TCD Alignment of 32 Bytes to support Scatter/Gather
2022-08-05 09:44:36 +08:00
David Sidrane
1421bc58db imxrt:Correct register usage in up_rtc_settime 2022-08-05 09:43:36 +08:00
David Sidrane
5e902861d9 imxrt:usdhc fix error when CONFIG_ARMV7M_DCACHE is off 2022-08-05 09:43:36 +08:00
David Sidrane
b9c6284750 imxrt:lowputc add extern "C" 2022-08-05 09:43:36 +08:00
Nathan Hartman
20bdd44e7b Remove executable permission from source and build files. 2022-08-04 12:48:18 -03:00
Xiang Xiao
8582a12388 drivers: Reorganize the power related code layout
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-04 10:28:28 +03:00
Masayuki Ishikawa
8e7752c7da arch: common: Fix up_check_tcbstack() for CONFIG_ARCH_ADDRENV=y
Summary:
- I noticed that ps shows incorrect stack usage when running
  getprime in the background.
- With CONFIG_ARCH_ADDRENV=y, a user task including pthread
  allocates its stack in the user space that needs to be
  accessed with a correct address environment.
- This commit fixes this issue.

Impact:
- CONFIG_ARCH_ADDRENV=y only

Testing:
- Tested with sabre-6quad:knsh on qemu-6.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-08-04 11:13:16 +08:00
Eero Nurkkala
e0291b1ce8 risc-v/mpfs: usb: configure fifos properly
RX_FIFO_ADDRs and TX_FIFO_ADDR were misconfigured. These addresses
overlapped causing data corruption during high USB loads. For
example, data corruption was present during the following conditions:

  1. Composite USB driver was used (CDC/ACM + Mass storage)
  2. /dev/ttyACM0 was accessed instantly from Linux side when
     starting up.
  3. Training data was sent to /dev/ttyACM0 from NuttX from the
     very beginning periodically.

It was observed that while Mass storage was negotiating, sometimes
data sent from NuttX to Linux via CDC/ACM was corrupt, although it
was sent properly on the TX fifo.

Also, don't access TXCSRL_REG_EPN_TX_FIFO_NE_MASK for EP0 as it's
not applicable.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-03 23:44:12 +08:00
raiden00pl
981ad9fc1e arch/stm32xx/Kconfig: simplify PWM options and unify them among stm32 chips 2022-08-03 23:43:19 +08:00
raiden00pl
935f110438 arch/stm32f7/stm32_tim.c: include the missing RCC header 2022-08-03 23:42:52 +08:00
raiden00pl
47dbad0a8b arch/stm32/stm32_foc.c: fix some ADC and PWM ifdefs 2022-08-03 23:42:37 +08:00
Peter van der Perk
a6da6dcec6 LPC17_40 CAN driver SocketCAN support 2022-08-03 17:58:57 +08:00
chao.an
d501e01eef arm/backtrace: use sp unwind if FRAME_POINTER is enabled on thumb mode
GCC toolchain Bug 92172 - ARM Thumb2 frame pointers inconsistent with clang

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-08-03 17:58:36 +08:00
Peter Bee
f20cd0295f arch: fix typo
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2022-08-03 17:37:08 +08:00
ligd
8c1fd1df81 rptun: update rptun to openamp 2022.04.0
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-08-03 01:22:53 +08:00
Daniel P. Carvalho
40e6c8dca4 STM32L4 DAC: Added basic support for low level operations 2022-08-02 10:43:59 +08:00
Jari van Ewijk
a554b9ce89 NXP S32K1XX: fix LPI2C reset 2022-08-01 07:34:03 -04:00
Xiang Xiao
c26bb35843 Remove the private NULL, TRUE and FALSE macros
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-31 22:12:57 +03:00
Sergey Nikitenko
ec59125ad3 stm32wb/mbox: fixing ACL transmit buffer 2022-07-31 10:29:29 +08:00