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17912 Commits

Author SHA1 Message Date
Abdelatif Guettouche
55a210d305 arch/xtensa/esp32_textheap.c: When allocating text prioritize alloacting 
from the RTC heap.  If that's not available fall back to the IRAM heap.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
1e49f2929f arch/xtensa/src/esp32: Extract the IRAM region as a separate heap. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
1719e9df94 arch/xtensa/esp32: Add the RTC Slow memory as a separate heap. 
This memory region can be accessed by both I & D buses, so the heap can
be used for data storage and code execution.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
6582c19904 arch/xtensa/src/esp32/hardware/esp32_soc.h: Add a function to check if a 
buffer comes from the RTC Slow memory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
a4289c4f84 xtensa/esp32_aes.c: Use the same output when testing the AES driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-21 06:23:55 -05:00
Masayuki Ishikawa
841fb02ac0 arch: esp32: Replace getcoreid with the latest esp-idf's 
Summary:
- I noticed that the getcoreid macro in the latest esp-idf
  is much simpler than the current NuttX's.
- This commit replaces the macro with the latest esp-idf's

Impact:
- SMP only

Testing:
- Tested with esp32-devkitc:wapi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-21 06:21:39 -05:00
Alexander Lunev
f7c8875fd7 sdio,stm32h7: fixed an issue with not starting IDMA data transfer in case of IO_RW_EXTENDED command (CMD53); 
corrected setting SDMMC_DCTRL.DTMODE field for block data transfers ending on block count
and for block data transfers ending with STOP_TRANSMISSION command;
stm32_sdio: added more debug messages
 2021-06-21 02:47:46 -05:00
Liu Han
2dd081ed7d risc-v/esp32c3: Support ESP32-C3 SHA accelerator 2021-06-21 02:41:53 -05:00
chenwen
8648970994 esp32&esp32c3/wifi: Fix the issues of Wi-Fi configuration being overwritten 2021-06-19 08:00:35 -03:00
chenwen
ee3350ed1d risc-v/esp32c3: Disable Wi-Fi reconnect by default 2021-06-19 08:00:35 -03:00
chenwen
c3792f0aae xtensa/esp32: Support ESP32 RTC driver 2021-06-18 22:01:34 -05:00
Xiang Xiao
ab974edc84 sched: Identify the stack need to free by TCB_FLAG_FREE_STACK 
instead calling kmm_heapmember or umm_heapmember because:
1.The stack supplied by caller may allocate from heap too
2.It's hard to implement these two function in ASan case

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I196377822b7c4643ab4f29b7c1dc41dcd7c4dab1
 2021-06-18 05:44:41 -07:00
Abdelatif Guettouche
af5e0c620f Rename MODULE_TEXT to TEXT_HEAP as the latter is more generic. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 07:14:17 -05:00
Abdelatif Guettouche
79e9347551 arch/risc-v/esp32c3/esp32c3_modtext.c: Prioritise allocation from the 
RTC heap when available.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
f54804bafc arch/risc-v/esp32c3: Create a separate heap for the RTC memory. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
7198b3ef4b risc-v/esp32c3/esp32c3_soc.h: Add a function to check if a pointer is 
within the RTC RAM range.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Daniel P. Carvalho
91e82d1597 Changed the STM32 Analog Comparator driver. 2021-06-18 00:50:24 -05:00
Sara Souza
00edeee1ff xtensa/esp32: Adds I2C Bit banging reset 2021-06-18 00:48:27 -05:00
Masayuki Ishikawa
83ac6cd399 arch: xtensa: Remove ISYNC from xtensa_compareset() 
Summary:
- According to the Xtensa ISA document, this ISYNC instruction
  between WSR SCOMPARE1 and S32C1I is unnecessary

Impact:
- SMP only

Testing:
- Tested with esp32-devkitc:wapi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-17 09:58:29 -05:00
Masayuki Ishikawa
2d016f8d21 arch: xtensa: Fix the PS register handling 
Summary:
- I noticed that DEBUGASSERT sometimes happens in nxsem_wait()
  when testing Wi-Fi with esp32-devkitc:wsifi_smp
- The call stack was not from an interrupt handler and actually
  g_current_regs[] were correct, even though asserted with
  (up_interrupt_handler() == false)
- Finally, I found that we need to call rsync after we set
  a new value to the PS register which is described in the
  Xtensa document.
- This commit fixes this issue

Impact:
- All xtensa architectures

Testing:
- Tested with esp32-devkitc:wifi_smp and esp32-devkitc:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-17 09:58:29 -05:00
Sara Souza
8f59054ef2 risc-v/esp32c3: Adds I2C RESET support via hardware. 2021-06-16 21:22:26 -05:00
Michal Lenc
6dc3c3d1b2 arch/arm/src/imxrt: fix nxstyle warnings and errors 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-06-16 21:22:03 -05:00
Michal Lenc
7bcd50955f arch/arm/src/imxrt: add missing clock to imxrt_xbar.c and fix usage of imxrt_enc.c while debug option is enable 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-06-16 21:22:03 -05:00
Janne Rosberg
673f9519eb risc-v/mpfs: add dma support 2021-06-16 12:22:54 -05:00
Eero Nurkkala
502210e98c riscv/mpfs: add i2c reset handler 
Add reset functionality into the mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-16 12:31:36 -03:00
Liu Han
04c805207a risc-v/esp32c3: Support ESP32-C3 efuse 2021-06-16 09:35:09 -03:00
retogaeh
f109a96ad2 Update arch/arm/src/stm32h7/stm32_adc.c 
Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>
 2021-06-16 04:58:06 -07:00
GAEHWILER Reto
b9fba3edae stm32h7 fix adc port to handle overrun and the DR's fifo, adapt adc driver 
* port didn't know about data-register fifo
* port didn't handle overrun condition
* driver could get stuck if interrupts were skipped due to saturation
 2021-06-16 04:58:06 -07:00
Virus.V
69fce77718 risc-v/bl602: update firmware to fix undefined up_irq_* symbols when linking 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-15 23:25:16 -05:00
Dong Heng
60fb1adaca riscv: Add inline IRQ process functions 
Remove functions from RISC-V chips.
 2021-06-15 23:25:16 -05:00
Xiang Xiao
2e49e1bc5c mtd: Add MTDIOC_FLUSH IOCTL like MTDIOC_XIPBASE 
since the old design reuse BIOC_FLUSH for
MTD device which make some confusion

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-15 13:26:45 -03:00
Sara Souza
2a7b97c0cd risc-v/esp32-c3: Adds I2C polled support 2021-06-15 10:51:18 -05:00
Daniel P. Carvalho
4b351fc447 Adds PWM example to nucleo-g431kb board. 2021-06-14 18:45:04 -03:00
Liu Han
8eaaf6d462 risc-v/esp32c3: Support ESP32-C3 RSA accelerator 2021-06-14 15:03:11 -03:00
Yuichi Nakamura
9b8e81ebc1 arm/rp2040: Fix warnings when UART console is not used 2021-06-14 09:05:19 -03:00
Yuichi Nakamura
b860e3c4ad arm/rp2040:USB device controller support 
Summary:
- Add Raspberry Pi Pico (RP2040) USB device controller support.
- Confirmed that CDC/ACM, MSC and these composite device are working.
- The current implementation have an unresolved issue and some workaround
  for USB MSC SCSI driver is required.
  See the comment in the patch "usbmsc: Add USBMSC_NOT_STALL_BULKEP for RP2040 workaround".

Impact:
- RP2040 only

Testing:
- Tested with Windows 10 and Ubuntu-18.04/20.04 as the USB host.
- Tested configurations:
  - raspberrypi-pico:usbnsh
  - raspberrypi-pico:usbmsc
  - raspberrypi-pico:composite
 2021-06-14 09:05:19 -03:00
Sara Souza
7300bc8f1c xtensa/esp32: Adds I2C polled support. 2021-06-13 05:04:51 -05:00
Masayuki Ishikawa
bafac8b560 arch: k210: Fix stack coloring for the idle thread stack 
Summary:
- I noticed that stack coloring for the idle thread stacks does
  not work due to the recent changes
- This commit fixes this issue

Impact:
- k210 only

Testing:
- Tested with both maix-bit (dev board) and QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-12 05:54:08 -05:00
Eero Nurkkala
1bce864ef7 mpfs: add i2c driver 
This adds mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-11 21:03:42 -05:00
Daniel P. Carvalho
361703a881 Added basic support for nucleo-g431kb board. 2021-06-11 20:51:56 -05:00
Eero Nurkkala
fad34e04c4 mpfs: add spi driver 
This adds the SPI driver for the MPFS Icicle board.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-11 09:10:03 -05:00
Abdelatif Guettouche
96bcf7678b risc-v/esp32c3_wifi_adapter.c: Remove a config that's only used in 
Xtensa chips.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-11 10:49:52 -03:00
Jiuzhu Dong
2fd25d7ea7 arch/armv7-a: Colorize the idle thread stack for other cpu(SMP) 
Keep previous modification.

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-06-11 01:26:50 -05:00
raiden00pl
d76f8ea04a arch/arm/src/stm32/stm32_foc.c: add workaround for an issue found in STM32G4 family 
From G4 erratas: "ADC channel 0 converted instead of the required ADC channel"
 2021-06-10 13:58:33 -03:00
raiden00pl
7c47f32a19 arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h: rename OPAMP pins to match the manual 2021-06-10 13:58:33 -03:00
raiden00pl
76824ba2a9 stm32g4xxxx_memorymap.h: remove invalid OPAMP1-6 definitions 2021-06-10 13:58:33 -03:00
raiden00pl
af0f2b4f37 stm32g4: add OPAMP defs 2021-06-10 13:58:33 -03:00
Alexander Vasiljev
9d0da9818c arch/arm/src/stm32h7: qspi use indirect write instead indirect read without data. 2021-06-10 10:46:34 -05:00
Virus.V
7c20199a61 riscv/bl602:replace syslog to debugging log macros 2021-06-10 08:59:16 -05:00
Fotis Panagiotopoulos
2ef90786c8 setjmp.h: Added missing include. 2021-06-10 08:58:52 -05:00
Xiang Xiao
c0fdddc5d7 arch: Remove all go_nx_start from chip specifc source 
since the idle stack color is done in the common code now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-10 06:50:41 -07:00
Xiang Xiao
fa0d123f87 arch: Colorize the idle thread stack in an unified way 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Idae8da53e5a4799a8edc0e882f17fd515b70cb14
 2021-06-10 06:50:41 -07:00
Chen Wen
dbf9c87a42 risc-v/esp32c3: Support ESP32-C3 RTC driver 2021-06-10 09:33:04 -03:00
Alexander Vasiljev
45672c269d Make: use gcc as LD 2021-06-10 03:43:18 -07:00
Peter van der Perk
3b94669b7f FlexCAN Fix TX abort process 2021-06-09 13:34:13 -05:00
Xiang Xiao
6576306bca arch: Rename xxx_getsp to up_getsp 
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-09 10:20:02 -07:00
Juha Niskanen
939e547ca8 arch/arm/src/stm32l4: fix some printf format errors and warnings 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-06-09 11:52:33 -05:00
Xiang Xiao
5b2a17b892 Include assert.h in necessary place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-08 13:06:08 -07:00
David Sidrane
131e2490c9 stm32f7:bbsram add assert header 2021-06-08 13:19:22 -05:00
David Sidrane
a1de902708 stm32h7:bbsram add assert header 2021-06-08 13:19:22 -05:00
unixjet
68f19a6290 risc-v/rv32m1: Basic port to rv32m1 ri5cy 2021-06-05 17:25:57 -03:00
Gustavo Henrique Nihei
0b3c2c7603 spi: Refactor SPI Slave interface prefix to sync with I2C Slave 2021-06-05 04:50:34 -07:00
Gustavo Henrique Nihei
27782aca19 risc-v/esp32c3: Include missing debug.h header 2021-06-05 04:50:34 -07:00
Gustavo Henrique Nihei
77dfb39260 risc-v/esp32c3: Uniformize references to CPU interrupt ID 2021-06-04 23:26:13 +01:00
Gustavo Henrique Nihei
f53306f9af risc-v/esp32c3: Ensure internal linkage of interrupt map 2021-06-04 23:26:13 +01:00
Gustavo Henrique Nihei
a2bcffde73 risc-v/esp32c3: Remove unused macros 2021-06-04 23:26:13 +01:00
Abdelatif Guettouche
2d55f2659e riscv/esp32c3: Add module text allocator. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 18:08:36 -03:00
Abdelatif Guettouche
778e3ed4ad arch/risc-v/rv32im/riscv_assert.c: Provide dummy definitions of dump 
functions when ARCH_STACKDUMP is not enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 12:20:18 -05:00
Abdelatif Guettouche
94ded7a695 arch/riscv/rv32im/riscv_assert.c: Fix preprocessor condition. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 12:20:18 -05:00
Janne Rosberg
7b882c3588 risc-v/mpfs: fix ext irq 1-12 
Handle irq numbers 1-12 correctly
 2021-06-04 10:14:58 -05:00
Jani Paalijarvi
ebdc7a06b1 risc-v/mpfs: add MSTimer register offsets and bitmasks 2021-06-04 10:14:58 -05:00
Janne Rosberg
f7cbed0256 risc-v/mpfs: enable up_systemreset() 2021-06-04 10:14:58 -05:00
Janne Rosberg
ec11643394 risc-v/mpfs: add sysreg register defines 
This adds minimal set of sysreg defines for MPFS
 2021-06-04 10:14:58 -05:00
Masayuki Ishikawa
386946ee54 arch: cxd56xx: Fix address mapping in cxd56_modtext.c 
Summary:
- I noticed that DEBUGASSERTION() happens when executing
  an ELF application
- This commit fixes this issue by re-mapping the address
  to SYSBUS in up_module_text_free()

Impact:
- None

Testing:
- Tested with spresense (both DEBUG_ASSERTIONS=n and y)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-04 01:40:37 -05:00
Masayuki Ishikawa
f0b689a063 arch: arm: Add select ARCH_HAVE_MODULE_TEXT to ARCH_CHIP_CXD56XX 
Summary:
- I noticed that make savedefconfig shows warnings regarding
  'unmet direct dependencies (ARCH_HAVE_MODULE_TEXT)'
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with spresense:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-04 01:40:37 -05:00
Jaroslav Beran
d13be4ea57 samv7/spi: Allow 16-bit word size in spi_send 
Signed-off-by: Jaroslav Beran <jara.beran@gmail.com>
 2021-06-03 21:33:52 -05:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:36:03 -07:00
Kazuya Hioki
038941b11d arch: cxd56xx: Fix a register name in cxd56_sdhci.c 
Signed-off-by: Kazuya Hioki <Kazuya.Hioki@sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
cfe6e313fb arch: cxd56xx: Introduce up_testset2 in cxd56_testset.c 
Summary:
- In cxd56xx, ldrex/strex behavior is slightly different from
  other Arm architectures. Dummy strex must be issued to release
  the exclusive load & store unit.

Impact:
- SMP only

Testing:
- Tested with spresense:smp
- Tested with spresese:wifi_smp, spresense:rndis_smp
- NOTE: CONFIG_CXD56_TESTSET=y must be removed from defconfigs

Signed-off-by: Kazuya Hioki <Kazuya.Hioki@sony.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
2fc6361231 arch: cxd56xx: Introduce CXD56_PHYSADDR 
Summary:
- This commit converts data to the physical address for DMA transfer.

Impact:
- cxd56_dmac.c, cxd56_sdhci.c, cxd56_usbdev.c
- cxd56_cisif.c, cxd56_emmc.c, cxd56_ge2d.c, cxd56_udmac.c

Testing:
- Tested with following configurations
- spresense:wifi, spresense:wifi_smp, spresense_rndis, spresense_rndis_smp
- NOTE: additional commits are needed for the test
- NOTE: cxd56_cisif.c, cxd56_emmc.c, cxd56_ge2d.c, cxd56_udmac.c are not tested

Signed-off-by: Kazuya Hioki <Kazuya.Hioki@sony.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
a6572fc8c9 arch: cxd56xx: Use uintptr_t for srcend/dstend in dma_descriptor_s 
Summary:
- This commit uses uintptr_t for srcend/dstend in dma_descriptor_s

Impact:
- None

Testing:
- N/A

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
4ba5740c6e arch: cxd56xx: Introduce CONFIG_CXD56_USE_SYSBUS in Kconfig 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
8c97db37e0 arch: cxd56xx: Introduce cxd56_modtext.c 
Summary:
- This commit introduces cxd56_modtext.c to allocate a separate
  text memory for ELF

Impact:
- None

Testing:
- Tested with spresense:elf

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
588deffb6c arch: cxd56xx: Adjust loops per msec for the new memory map 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Xiang Xiao
281921bcf9 arch: Flush syslog buffer for sim and x86_64 arch 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:27:24 +09:00
David Sidrane
9b29641bf5 s32k1xx:eeprom fix missing debug.h 2021-06-02 17:36:06 -03:00
Sara Souza
7dd131b4c1 xtensa/esp32: Fixes support for HW flow control 2021-06-02 09:55:50 -05:00
Sara Souza
a54fe4ee1e xtensa/esp32-s2: Add support for serial HW flow control. 2021-06-01 21:37:37 -05:00
Sara Souza
b54be4e946 risc-v/esp32-c3: Add support for HW flow control. 2021-06-01 21:37:27 -05:00
Gustavo Henrique Nihei
24c206b3f8 risc-v/esp32c3: Add DMA support for the SPI Slave controller 2021-06-01 21:37:09 -05:00
Gustavo Henrique Nihei
15a93ae974 risc-v/esp32c3: Remove Master-only settings on SPI Slave driver 2021-06-01 21:37:09 -05:00
Alan C. Assis
929a4a7278 Fix dangling whitespace at the end of line 2021-06-01 07:49:54 +02:00
Sara Souza
f1d653c08c xtensa/esp32-s2: Adds support for serial driver, lowputc and termios. 2021-06-01 07:49:54 +02:00
Alan C. Assis
06795a221a Clean ESP32S2 Xtensa files 2021-06-01 07:49:54 +02:00
Abdelatif Guettouche
fccd5fbdd2 esp32s2_allocateheap.c: Use the address of the ROM data from the ROM linker script. 2021-06-01 07:49:54 +02:00
Alan C. Assis
7767acd24a Add initial ESP32S2 Xtensa support 2021-06-01 07:49:54 +02:00
Xiang Xiao
d7f96003cf Don't include debug.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-01 06:42:02 +09:00
Gustavo Henrique Nihei
1530b0f639 risc-v/esp32c3: Fix overwriting of registered-but-disabled interrupts 2021-05-31 09:15:40 -05:00
Gustavo Henrique Nihei
da78cf78eb risc-v/esp32c3: Remove useless parameter from DMA macro 2021-05-31 09:14:14 -05:00
chao.an
99bfd355c7 serial/uart/h4: add bt h4 uart serial driver 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-05-31 09:50:54 -03:00
chao.an
6c69b12000 wireless/bluetooth: decoupling bt_driver_s and bt_buf_s 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-05-31 09:50:54 -03:00
chao.an
6837d4e1ba arch/sim: remove BT uart implement 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-05-31 09:50:54 -03:00
Gustavo Henrique Nihei
7e15d897bd risc-v/esp32c3: Add driver for SPI Slave controller 2021-05-31 12:54:15 +01:00
chenwen
1d1dd8512f esp32&esp32c3/wifi: Support specific channel and bssid scan 2021-05-31 11:09:19 +01:00
Alin Jerpelea
02b244cb6f arch: arm: update licenses to Apache 
Sebastien Lorquet has submitted the CLA

Uros Platise has submitted the CLA

Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Alin Jerpelea
7e84ea3104 arch: renesas: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Alin Jerpelea
3b87c32bcc arch: or1k: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Alin Jerpelea
5a37ddfbe6 arch: misoc: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Jiuzhu Dong
dab99acfe3 sim/rptun: support multi(>2) core interactive by share memory 
N/A

Change-Id: Ia8254bfe369e40a04ed54adfa64afa38974b165c
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-30 23:28:40 -05:00
Abdelatif Guettouche
45d01ae2a8 arch/xtensa/esp32_emac.c: Call phy_enable_interrupt correctly. 2021-05-28 20:46:27 -03:00
Han Raaijmakers
04d81b24e3 S32K1XX LSPI Double word up to 64 bits support 2021-05-27 11:37:46 -07:00
Abdelatif Guettouche
e29da149e3 arch/riscv/src/esp32c3/esp32c3_rt_timer: Fix typos and re-word some 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
08aa9ce540 arch/xtensa/src/esp32/esp32_rt_timer: Fix typos and re-word some 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
0f3d94e8e8 arch/risc-v/src/esp32c3/esp32c3_rt_timer.h: Add section headers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
f24a687f8e arch/xtensa/src/esp32/esp32_rt_timer.h: Add section headers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Virus.V
c6317650f9 risc-v/bl602: Add RTC support 2021-05-26 20:03:19 -03:00
Gustavo Henrique Nihei
1d940b2982 risc-v/esp32c3: Constify DMA descriptor pointer to buffer 2021-05-26 14:05:27 -03:00
Gustavo Henrique Nihei
29cae80533 risc-v/esp32c3: Fix DMA TX Burst being set to input register 2021-05-26 14:05:27 -03:00
Dong Heng
73dcbac09d riscv/esp32c3: Add ESP32-C3 AES driver 2021-05-25 11:02:59 -03:00
Masayuki Ishikawa
88c6524d7c arch: imx6: Add termios support to imx6 
Summary:
- This commit adds termios support to imx6

Impact:
- None

Testing:
- Tested with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-05-25 07:17:29 -05:00
Govind Singh
2975050c96 arch/riscv/bl602: Fix typo in i2c driver 
Signed-off-by: Govind Singh <govind.sk85@gmail.com>
 2021-05-25 01:37:28 -05:00
Janne Rosberg
d6205642ab add support for PolarFire SoC and icicle board 
Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-05-24 22:55:44 -05:00
Sara Souza
3144a5a272 xtensa: Fixes names of serial functions 2021-05-24 10:04:50 -05:00
Xiang Xiao
001e7c3e76 sched: Don't include nuttx/sched.h inside sched.h 
But let nuttx/sched.h include sched.h instead to
avoid expose nuttx kernel API to userspace.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-05-24 12:11:53 +09:00
Dong Heng
76df958e34 riscv/esp32c3: Support SPI Flash encryption read/write 2021-05-23 08:37:25 -03:00
David Sidrane
86523318fc stm32f7:i2c use inttypes 2021-05-22 08:53:07 -05:00
David Sidrane
8596fdd0bf stm32h7:i2c use inttypes 2021-05-22 08:53:07 -05:00
Alan C. Assis
1a84314f5d xtensa: #ifdef SYMBOL is always true if SYMBOL defined as 0 2021-05-22 08:35:12 -05:00
Huang Qi
f4a0b7aedd libc: Call pthread_exit in user-space by up_pthread_exit 
Drop to user-space in kernel/protected build with up_pthread_exit,
now all pthread_cleanup functions executed in user mode.

* A new syscall SYS_pthread_exit added
* A new tcb flag TCB_FLAG_CANCEL_DOING added
* up_pthread_exit implemented for riscv/arm arch

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-05-21 22:46:52 -06:00
Huang Qi
81a01d089b libc/pthread: Fix comment and document issue 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-05-21 22:46:52 -06:00
Gregory Nutt
bb9b58bdde libc: Move pthread_create to user space 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Change-Id: I5c447d94077debc79158686935f288e4c8e51e01
 2021-05-21 22:46:52 -06:00
chao.an
6c40185985 arm/v7-a/fpu: add VFP-v3 D32 support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-05-21 09:55:00 -03:00
Jukka Laitinen
e4fd99682e rv64gc: use PRIx64 format for alert and assert 
This fixes compilation warnings caused by number formatting

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-05-20 05:42:01 -05:00
Jukka Laitinen
e79a45bb93 rv64gc/riscv_assert.c: Fix compilation without CONFIG_DEBUG_ALERT 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-05-20 05:42:01 -05:00
Anthony Merlino
c9ccbb9e03 stm32h7xxxx_rcc.c: Fixes typo in comment 2021-05-20 00:53:49 -07:00
Anthony Merlino
35553147ba stm32h7 rcc: Sync h7x7xx and h7x3xx. Changes are relevant to both 2021-05-20 00:53:49 -07:00
SPRESENSE
6b5a4cbfd3 arch: cxd56xx: Fix parameter check of hostif buffer 
Fix a parameter check of the buffer attribute in opening hostif driver.
 2021-05-20 07:23:48 +02:00
SPRESENSE
db9c94962b arch: cxd56xx: Add host interface driver 
Add host interface driver which supports I2C or SPI slave feature.
 2021-05-20 07:23:48 +02:00
SPRESENSE
5a7a118320 arch: cxd56xx: Fix uninitialized variable for gnss driver 
Fix uninitialized variable in gnss driver.
CodeSonar Warning 518288 - 518292
 2021-05-20 07:23:48 +02:00
SPRESENSE
151fec4e98 arch: cxd56xx: Do not re-initialize the console for subcore 
If the subcore configuration, which is mainly used in the Spresense
Arduino environment, is enabled, the serial console has been already
initialized by maincore. Then, don't need to re-initialize the UART1
serial driver.
 2021-05-20 07:23:48 +02:00
SPRESENSE
efd4789b72 arch: cxd56xx: gauge: Use the dedicated debug macro 
Replace to the battery dedicated debug macro instead of standard one.
 2021-05-20 07:23:48 +02:00
SPRESENSE
50cb0306b6 arch: cxd56xx: charger: Use the dedicated debug macro 
Replace to the battery dedicated debug macro instead of standard one.
 2021-05-20 07:23:48 +02:00
SPRESENSE
bb348cc464 arch: cxd56xx: gnss: Fix compile error in debug log 
Fix compile error when debug log is enabled.
Replace debug message from obsolete logerr() to _err().
 2021-05-20 07:23:48 +02:00
SPRESENSE
6d3fb9ee81 arch: cxd56xx: wdt: Fix compile error in debug log 
Fix compile error when CXD56_WDT_REGDEBUG is enabled.
 2021-05-20 07:23:48 +02:00
SPRESENSE
f0cae6cdf3 arch: cxd56xx: Fix multiple open and close ADC driver 
ADC driver does not support multiple open and close. It causes the memory
corruption by multiple free. This commit fixes this problem by introducing
the reference counter.
 2021-05-20 07:23:48 +02:00
SPRESENSE
98871e58af arch: cxd56xx: Fix gnss open error by clock change 
If the system clock is changed during loading gnssfw, gnss open may be
failed. So this commit prohibits clock change until loading gnssfw is
completed.
 2021-05-20 07:23:48 +02:00
SPRESENSE
e26da5f564 arch: cxd56xx: Update isop firmware 
Update isop firmware which supports for the error handling and i2c
multi-master environment.
 2021-05-20 07:23:48 +02:00
SPRESENSE
f548ffa7a7 arch: cxd56xx: Support execution error by SCU sequencer 
Enable interrupt by SCU sequencer execution error. If the interrupt
occurs, then it stops the sequencer and returns the error code.
 2021-05-20 07:23:48 +02:00
SPRESENSE
ba6201401f arch: cxd56xx: Remove unnecessary i2c settings 
Remove slave address register setting that is unnecessary for the
transfer by SCU sequencer.
 2021-05-20 07:23:48 +02:00
SPRESENSE
ade26c17d2 arch: cxd56xx: Update i2c register initialization 
Enable RX_FIFO_FULL_HLD_CTRL and RESTART of i2c control register in
i2c initial settings for transfer by SCU sequencer.
 2021-05-20 07:23:48 +02:00