Comments only. No functional changes. See STM32G474 Reference Manual
(RM0440 Rev 4), section 3.4.1, Table 11, "Option byte organization."
arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h:
* STM32_OPTION_BASE: The comment incorrectly said the range was
0x1fff7800-0x1fff780f for a total of 16 Option Bytes. Corrected
this to 0x1fff7800-0x1fff782f, as the device has 48 Option Bytes
for this option block.
* STM32_OPTION_BASE2: The comment incorrectly said the range was
0x1ffff800-0x1ffff80f for a total of 16 Option Bytes. Corrected
this to 0x1ffff800-0x1ffff82f, as the device has 48 Option Bytes
for this option block.
Summary:
- This commit improves SPI performance.
- For small data, it does not use DMA.
Impact:
- All use cases which use SPI with DMA
Testing:
- Tested with spresense:wifi and spresense:example_lcd
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes IRQ control for the following use case
- The gs2200m Wi-Fi driver requests SPI-DMA to receive a packet.
- cxd56_dma.c enables IRQ for the SPI-DMA and start transfer.
- Then LCD driver requests SPI-DMA to display an image.
- These SPI-DMAs use different DMA channels but share the DMA controller.
- Also, they share the same IRQ.
- When the first SPI-DMA finishes the transfer, it disables the IRQ.
- And if the second SPI-DMA finishes the transfer just after the IRQ disabled.
- The second SPI-DMA will be in a deadlock condition.
- To resolve this issue, do not control IRQ during DMA transfer.
- Instead, up_enable_irq() is called in up_dma_initialize()
Impact:
- All use cases which use DMA
Testing:
- Tested with spresense:wifi with LCD
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
boards: metro-m4 Add support for starting the watchdog timer on the metro-m4.
Testing:
- Build check only
Signed-off-by: Leomar Mateus Radke <leomar@falker.com.br>
Summary:
- This commit adds SMP support to cxd56_farapi.c
- nxplayer now works in SMP mode
Impact:
- Spresense in SMP mode only
Testing:
- Add the following configs to spresense:wifi
- +CONFIG_SCHED_INSTRUMENTATION=yy
- +CONFIG_SCHED_INSTRUMENTATION_BUFFER=y
- +CONFIG_SMP=y
- +CONFIG_SMP_NCPUS=2
- +CONFIG_SPINLOCK_IRQ=y
- Run nxplayer and play an WAV file on uSD card
- NOTE: http streaming playback would cause deadlocks
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Fixes:
##[error]net/tun.c:837:13: error: conflicting types for 'tun_poll_expiry'
837 | static void tun_poll_expiry(FAR void *arg)
| ^~~~~~~~~~~~~~~
net/tun.c:196:13: note: previous declaration of 'tun_poll_expiry' was here
196 | static void tun_poll_expiry(wdparm_t arg);
| ^~~~~~~~~~~~~~~
And
##[error]net/tun.c:881:57: error: passing argument 4 of 'wd_start' makes integer from pointer without a cast [-Werror=int-conversion]
881 | wd_start(&priv->txpoll, TUN_WDDELAY, tun_poll_expiry, priv);
| ^~~~
| |
| struct tun_device_s *
In file included from /github/workspace/sources/nuttx/include/nuttx/sched.h:41,
from /github/workspace/sources/nuttx/include/sched.h:34,
from /github/workspace/sources/nuttx/include/nuttx/arch.h:81,
from net/tun.c:60:
/github/workspace/sources/nuttx/include/nuttx/wdog.h:134:42: note: expected 'wdparm_t' {aka 'long unsigned int'} but argument is of type 'struct tun_device_s *'
134 | wdentry_t wdentry, wdparm_t arg);
| ~~~~~~~~~^~~
And
chip/cxd56_rtc.c: In function 'up_rtc_initialize':
##[error]chip/cxd56_rtc.c:358:3: error: too many arguments to function 'cxd56_rtc_initialize'
358 | cxd56_rtc_initialize(1, NULL);
| ^~~~~~~~~~~~~~~~~~~~
chip/cxd56_rtc.c:253:13: note: declared here
253 | static void cxd56_rtc_initialize(wdparm_t arg)
| ^~~~~~~~~~~~~~~~~~~~
boards: metro-m4 Add support for starting the watchdog timer on the metro-m4.
Testing:
- Build check only
Signed-off-by: Leomar Mateus Radke <leomar@falker.com.br>
to save the preserved space(1KB) and also avoid the heap overhead
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I694073f68e1bd63960cedeea1ddec441437be025
Interrups were blocked 1*n/baud Seconds. The former comment indicates
there was an asumption that the TXE would be set at DMA completion.
In reality this is not true. There can be 1 char in the TX Shift
register and one in the TX holding register, when DMA completes.
Waiting on TXE is not needed at all. The DMA will resume on the
DMA req when the TX holding register is written to the TX Shift
register.
