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219 Commits

Author SHA1 Message Date
chao.an
7c02432f0e arm/armv7-a/r: set the default CPU mode to System 
In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 19:54:53 +09:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Petro Karashchenko
fc9e2d272e arch/arm/arm[-a|-r]: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-11 11:08:01 +08:00
zhuyanlin
5af1b671b6 armv7-a/armv7-r:cache: modify hardcode in cache set/way operation 
Some chip not use the default cache size & way , read from
CCSIDR instead of hardcode.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-03 14:11:31 +08:00
Xiang Xiao
087b9e5ff3 arch: Move the content from svcall.h to syscall.h 
and remove svcall.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-27 22:54:13 +08:00
chao.an
b57e0b6118 arm/armv7-a/r: check ARMV7A_DECODEFIQ on dataabort 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-27 17:25:22 +09:00
chao.an
c369e47107 arm/armv7-a/r: handle swi on interrupt stack 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-27 17:25:22 +09:00
chao.an
13889ba868 arch/arm: unify some duplicate code to common layer 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 21:35:55 +08:00
chao.an
db3a40ac25 arch/armv7-r: unify switch context from software interrupt 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 15:04:29 +09:00
chao.an
e0fabbfdd6 arch/arm: replace SYS_syscall_return hardcode from syscall 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-22 17:59:02 +08:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 20:10:14 +01:00
Oki Minabe
19e5c8f6d3 armv7-a/r: fix SVC's sp restore in arm_vectors.S 2022-02-20 18:39:30 +08:00
Oki Minabe
c1ea37742b fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
zhuyanlin
3ab65f9b08 armv7-a/r: use flush/clean_all if size large than cache size 
For cache flush/clean performance

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-09 18:16:31 +01:00
zhuyanlin
4eba2f3527 armv7-a/r:cache: add cp15_cache_size function 
Add cp15_cache_size function for armv7-a/r

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-09 18:16:31 +01:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit" 
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-09 21:21:43 +08:00
zhuyanlin
cc8ab23550 armv7-r/a: fix a4 register use in xxx_invalidate/flush/clean_all.S 
Use sub loop instead of add loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-08 19:39:43 +09:00
Xiang Xiao
2c3020ddaf arch/Toolchain.defs: Replace --print-file-name=libgcc.a with --print-libgcc-file-name 
to more compatable with clang: https://reviews.llvm.org/D25338

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-31 09:46:04 +01:00
Xiang Xiao
e0b62bf677 arch/Toolchain.defs: Don't expand EXTRA_LIBS immediately 
since board's Make.defs may overwrite ARCHCPUFLAGS

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-30 11:04:35 +09:00
Xiang Xiao
1c2c0e4707 arch/Toolchain.defs: Simplify the builtin library addition for EXTRA_LIBS 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-28 12:02:38 +01:00
Xiang Xiao
f903a55102 sched/tcbinfo: Fix the compile warning 
Update tcbinfo struct

armv8-m/arm_tcbinfo.c:109:3: warning: excess elements in struct initializer
  109 |   TCB_REG_OFF(REG_S31),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:109:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:110:3: warning: excess elements in struct initializer
  110 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:110:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:111:3: warning: excess elements in struct initializer
  111 |   TCB_REG_OFF(REG_FPSCR),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:111:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:112:3: warning: excess elements in struct initializer
  112 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:112:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:37:1: warning: missing braces around initializer [-Wmissing-braces]
   37 | {

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-27 17:36:27 +08:00
zhuyanlin
644c2be3aa armv7-a/r:cache: implemention clean&flush_dcache_all 
For armv7-a/r cache:
And clean_dcache_all, flush_dcache_all

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-27 15:15:28 +08:00
zhuyanlin
4d5c2586a9 armv7-a/r:cp15_invalidate_dcache_all: fix Sets mask error. 
As NumSets field is bits 13-27, use 0x7fff instead.
And add way to get from CCSIDR.
 2022-01-27 15:13:08 +08:00
Petro Karashchenko
6c27f3c19d toolchain: add libm to EXTRA_LIBS only if it is provided by the compiler 
Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-22 15:36:29 +08:00
Xiang Xiao
2935751bfd Fix error: implicit declaration of function 'up_cpu_index' 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 23:21:21 +08:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-16 11:11:14 -03:00
Zeng Zhaoxiu
fb43fd73ed signal: signal handler may cause task's state error 
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.

Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
 2022-01-05 21:36:44 +09:00
chao.an
cf2dfa8985 arch/arm/assert: move the arm_assert to common code 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 05:09:30 -06:00
chao.an
579738c8fa arch/arm: move the backtrace implement to common code 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 03:02:01 -06:00
chao.an
a42aa8415d compile/flags: add FRAME_POINTER into Toolchain.defs 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-27 22:31:27 -06:00
chao.an
6069433d2d arch/arm/cortex-a/r: dump all registers with alias 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-23 06:54:32 -06:00
chao.an
a0b61bbf6f arm/cortex-a/r: enhance the task dump 
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-22 11:46:02 -03:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:02:12 -03:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump 
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-15 12:00:35 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow 
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 01:43:18 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-06 00:47:58 -06:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug. 
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-10 14:31:10 -03:00
David Sidrane
9d8f7126f6 armv7-m,armv7-r,armv8-m:MPU Add mpu_reset and ARM_MPU_EARLY_RESET 
When NuttX is booted from a foreign (non NuttX)
   bootloader. There as a possibility that the
   bootloader configured the MPU, in an
   incompatible way for the NuttX memory usage.

   The option to reset the MPU before it is initialized
   may not succeed if the bss and data initialization
   code violated the previous MPU configurations.

   Added herein are ARM_MPU_RESET and
   ARM_MPU_EARLY_RESET. The former can be used
   If the system is capable of booting and running
   NuttX MPU configuration code without an MPU
   violation. The latter is used if the system can
   not run the bss and data initialization code.

   These are options so that a NuttX may be configured to
   not clobber a bootloader MPU configuration in a system
   that is architected to share the MPU configuration task.
 2021-10-23 03:58:26 -05:00
YAMAMOTO Takashi
58bdcbab9b Revert "Make: use gcc as LD" 
This reverts commit 45672c269d.

Because:

* It's very confusing to have cc as LD.
* I don't see what "-nostartfiles -nodefaultlibs" in LDFLAGS are
  supposed to do when we use LD directly. It would be simpler to
  remove them from our LDFLAGS.
 2021-09-08 09:40:48 +08:00
YAMAMOTO Takashi
5ad1cba338 Revert "arch: Replace ar and nm with gcc-ar and gcc-nm" 
This reverts commit b05737d78f.

Because it broke clang-based builds.
 2021-09-07 10:54:15 +08:00
Xiang Xiao
b05737d78f arch: Replace ar and nm with gcc-ar and gcc-nm 
to make enable LTO easily

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-09-02 10:02:14 -03:00
Xiang Xiao
b0c782255c libxx: Change CXX_LIBSUPCXX to LIBSUPCXX 
align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-28 17:14:48 -03:00
chao.an
d5d6297ca1 arch/arm/assert: enhance the assert dump 
show the all tasks info including backtrace and registers

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 13:31:08 +08:00
chao.an
f14bd44001 arch/armv7: add up_backtrace support based on frame pointer 
This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory

This feature can not be used in THUMB2 mode if you are using GCC toolchain,
More details please refer:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 13:30:08 +08:00
Abdelatif Guettouche
5ff703d5d0 arch/*_testset: Fix few typos. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 00:20:20 +08:00
Abdelatif Guettouche
5b350f3a0f arch/*_reprioritizertr.c: Fix typos in comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-14 11:19:34 -07:00
ligd
aac0db368c ARM: fix CPSR corruption after exception handling 
It seems to be caused by the corrupted or wrong CPSR restored on return
from exception. NuttX restores the context using code like this:

    msr spsr, r1

GCC translates this to:

    msr spsr_fc, r1

As a result, not all SPSR fields are updated on exception return. This
should be:

    msr spsr_fsxc, r1

This bug has been fixed by Heesub Shin in:
343243c7c0

Change-Id: Ibc64db7bceecd0fb6ef39284fb5bc467f5603e2e
 2021-07-19 08:41:06 -03:00
Xiang Xiao
98b5724b59 arch: Fix rtcb can't found error 
use the same condition check in declaration and reference

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
 2021-07-16 12:48:09 -03:00
Xiang Xiao
fa0d123f87 arch: Colorize the idle thread stack in an unified way 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Idae8da53e5a4799a8edc0e882f17fd515b70cb14
 2021-06-10 06:50:41 -07:00
Alexander Vasiljev
45672c269d Make: use gcc as LD 2021-06-10 03:43:18 -07:00