lpc43/54 SDMMC: Wading through bits trying to make sense out of what is a event want interrupt which deal mostly with commands+responses and what is a data transfer event. DTO is the only wildcard. I think this clear now but DMA transfers will fail with CRC error.
lpc43/54 SDMMC: DTO is a wait event, not a transfer event.
lpc43/54 SDMMC: Significant simplication to previous design. More debug output.
lpc43/54 SDMMC: Don't allow duplicate events in waitmask and xfrmask.
lpc43/54 SDMMC: Not all interrupts were being disabled at the end of a transfer.
lpc43/54 SDMMC: Defer enabling DMA transfer interrupts until after command has been sent.
Squashed commit of the following:
arch/arm/src/lpc43xx: SDMMC driver now builds for the LPC43 (provided that the proper definitions appear in the board.h file).
arch/arm/src/lpc43xx: Update basic changes to the ported lpc54xx driver for lpc43xx clocking and GPIOs.
arch/arm/src/lpc43xx: Brings in the LPC54xx SD/MMC driver with absolutely no changes other than changing all occurences of 54 to 43.
arm/arm/src/lpc43xx: Add build support for the lpc54 SDMMC driver.
lpc54 SDMMC: Check for successful data transfer last. Checking first means that we miss errors.
Squashed commit of the following:
arch/arm/src/lpc54xx: SDMMC fixes.. DMA should not be enabled on non-DMA transfers, the burst setting in FIFOTH is supposed to match the burst setting in the BMOD reseters, Add DMA error interrupt support.
arch/arm/src/lpc54xx: Mostly costmetic changes to the SDMMC driver.
In lc823450, ldrex and strex are not supported. So we implemented
up_testset() with H/W Mutex. However, there was a bug in memory
access order. This change ensures correct memory access order in
up_testset() for lc823450.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
lc823450 http streaming
* arch/arm/src/lc823450: Use spinlock APIs in lc823450_gpio.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add a warning message in up_ack_irq()
In SMP mode, H/W interrupts should be handled on CPU0 to avoid deadlocks.
Other changes:
Fix a potential race condition in up_enable_irq()
Use spinlock APIs instead of critical section APIs.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Enable HRT_TIMER in lc823450_timerisr.c
Other changes:
Fix style violations and call up_enable_irq() to assign CPU0 for IRQ handling.
Use spinlock APIs instead of critical section APIs.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Fix race conditions in dma/usbdev.
In SMP mode, critical data must be protected explicitly.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt
Add notes on .gdbinit and networking. Update comments on SMP.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update defconfigs
Enable HRT_TIMER, LC823450_MTM0_TICK, SPINLOCK_IRQ
Enable NET_TCP_RWND_CONTROL, NXPLAYER_HTTP_STREAMING_SUPPORT (rndis only)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/lpc54xx: Adds the LPC54-specific clock configuration logic to the leveraged SD/MMC driver.
arch/arm/src/lpc54xx: Leveraged SD/MMC driver builds without error but is still missing clock configuration logic.
arch/arm/src/lpc54xx: Bring in LPC43xx SD/MMC driver from https://github.com/Smoothieware/smoothie-nuttx/tree/master/nuttx/arch/arm/src/lpc43xx
