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3918 Commits

Author SHA1 Message Date
Gregory Nutt
e1799b0423 Cortex-A/SAMA5 address environment support is code complete (untested) 2014-08-25 11:18:32 -06:00
Gregory Nutt
e0a48b60b6 Change naming of ELF interfaces from arch_ to up_ for consistency 2014-08-25 06:47:14 -06:00
Gregory Nutt
7aea220ebf After cached related fix, the ELF example is now functional 2014-08-24 14:12:45 -06:00
Gregory Nutt
10b621ac10 Modify ADDRENV Kconfigs. Z180 does not need all of the virtual address settings that the ARM does 2014-08-24 12:54:37 -06:00
Gregory Nutt
241a7e17bd addrenv interface changes: up_addrenv_create() may need to create .text and .bss/.data separately because of differing access privileges (read/execute vs read/write). And, as a consequence, up_addrenv_vaddr() needs to be split into up_addrenv_vtext(0 and up_addrenv_vdata(). 2014-08-24 11:54:14 -06:00
Gregory Nutt
2cb9d5c7b0 Add addrenv.h; First cut at Cortex-A address environment structures; Add configuration options to setup address enviornment 2014-08-24 09:57:53 -06:00
Gregory Nutt
1624e2fbcf Change CONFIG_ADDRENV to CONFIG_ARCH_ADDRENV; change how it is selected -- the architecure must first declare support 2014-08-24 06:42:11 -06:00
Gregory Nutt
03830250e7 ARMv7-A: Add skeleton environment and build support for process address environments 2014-08-23 18:59:24 -06:00
Gregory Nutt
3bd810b316 Add option to select 64-bit build platform 2014-08-22 18:21:32 -06:00
Gregory Nutt
081f88b4b9 STM32 serial: MAke uart_devs[] const. From Freddie Chopin 2014-08-22 16:20:52 -06:00
Gregory Nutt
4af3e1cfa1 Recent STM32 UART change: Wasn't that logic backward? Shouldn't that have been disable the USART if (1) we don't have than many USARTs OR (2) we don't have that particular USART -- not AND. 2014-08-22 16:16:23 -06:00
Gregory Nutt
e79d6e3c8b A few fixes for compilation errors due to recent address environment fixes 2014-08-22 15:55:00 -06:00
Gregory Nutt
4d029ee13b uintptr_t should be 64-bits under Cygwin64 2014-08-22 15:18:55 -06:00
Gregory Nutt
1d586e6136 An address environment is the property of a task group, not of a thread 2014-08-22 12:32:34 -06:00
Gregory Nutt
150fcfb5b8 STM32 F401: Only 3 USARTS, but need to set STM32_NUSARTS to six because they are not numbered sequentially 2014-08-22 09:02:58 -06:00
Gregory Nutt
de3dd8e96b STM32 F401: Correct support for USART6 on this chip. From Freddie Chopin 2014-08-22 06:49:16 -06:00
Gregory Nutt
ad9b3f8ab8 wdog.h does not contain any application interface, only internal OS interface. Further, it is non-standard. Move wdog.h from include/ to include/nuttx. For the same reason, move the description of the watchdog timer interfaces from the Users Guide to the Porting Guide. 2014-08-21 11:16:55 -06:00
Gregory Nutt
3b07378b38 NSH link management now works! The last fix was to the Ethernet drivers: They cannot disable clocking to the Ethernet blok on ifdown. Otherwise, we cannot communicate with the PHY 2014-08-17 17:54:46 -06:00
Gregory Nutt
004788d7c0 Change the way PHY interrupts work: disable automatically. Then we have to re-subscribe each time after the interrupt fires 2014-08-17 16:51:56 -06:00
Gregory Nutt
e04ab2bcfc In order to get PHY interrupts, they must be enabled at the PHY (still don't get PHY interrupts) 2014-08-17 13:03:18 -06:00
Gregory Nutt
5ba42680ac For all SAM Ethernet, need to enable management interface before reading PHY regisers in IOCTL 2014-08-17 11:09:54 -06:00
Gregory Nutt
ab78e8a0c5 SAM3/4 Ethernet: Clone ioctl support from the SAMA5 2014-08-17 06:54:37 -06:00
Gregory Nutt
d87013a665 Use the device name assigned by the registration process, not our best guess 2014-08-16 15:14:39 -06:00
Gregory Nutt
057af36c1d More of the PHY event notification logic change: Fix some compile errors when full feature is enabled; Add some missing ioctol logic 2014-08-16 15:04:09 -06:00
Gregory Nutt
68e55c454c Implement all network ioctls, including the new ioctl to setup PHY event notifications. 2014-08-16 14:09:14 -06:00
Gregory Nutt
f33510a394 Modified to support the change to the network ioctl signature changes. Also add support for new ioctl to setup PHY event notifications. 2014-08-16 14:08:58 -06:00
Gregory Nutt
c9ba1d4091 Fix conditional compilation error 2014-08-12 10:00:58 -06:00
Gregory Nutt
7025465109 Adds support for localtime. From Max Neklyudov 2014-08-12 06:18:22 -06:00
Gregory Nutt
56196ecea1 Fix a computation error in the fix for the last computational error 2014-08-11 12:07:49 -06:00
Gregory Nutt
51da249d0e Correct time conversion, 1000000 not 1000 to convert seconds to microseconds. 2014-08-11 11:14:10 -06:00
Gregory Nutt
f2058fa271 Comment out reassessment of timer in the middle of context switches. Need to revisit 2014-08-11 07:05:47 -06:00
Gregory Nutt
cd53f96f11 SAMA5 Tickless: Corrects some logic errors with timer/counter frequency 2014-08-10 19:04:18 -06:00
Gregory Nutt
8855c1369b Cosmetic 2014-08-10 16:09:45 -06:00
Gregory Nutt
c7a51f4ef1 Cosmetic changed, updated README files, improved comments 2014-08-10 13:11:31 -06:00
Gregory Nutt
71e18367f6 Don't try to return time remaining if the timespec pointer is NULL 2014-08-10 11:39:16 -06:00
Gregory Nutt
a5514be85c Move TC debug options to one file 2014-08-10 11:38:44 -06:00
Gregory Nutt
219c1a68d3 Update comments 2014-08-10 11:38:08 -06:00
Gregory Nutt
320707fdfa SAMA5: Fix bugs in timer/counter interrupts and one-shot timer 2014-08-10 10:47:38 -06:00
Gregory Nutt
6324df44e8 SAMA5 Timer/counter repair: Missing sem_post() caused a hang 2014-08-09 18:34:52 -06:00
Gregory Nutt
d1d1d76189 SAMA5: Use the one-shot and free-running timers to implement tickless OS support for SAMA5 2014-08-09 17:14:51 -06:00
Gregory Nutt
569d5d7218 SAMA5 free-running timer: Add support for a free-running timer wrapper around the low-level timer/counter logic. 2014-08-09 16:43:48 -06:00
Gregory Nutt
acb05460d0 SAMA5 oneshot: Some clean-up and correction to the initial implementation 2014-08-09 16:42:04 -06:00
Gregory Nutt
d8aa6c01bd SAMA5 timer/counter: Add support for a one-shot timer wrapper around the low-level timer/counter logic. This also involved several changes that rippled into the ADC driver (untested). 2014-08-09 15:27:55 -06:00
Gregory Nutt
5803fb78b8 SAMA5 T/C: Can now handle non-constant BOARD_MCK_FREQUENCY. Also now supports methods to attach user interrupt handlers 2014-08-09 10:30:45 -06:00
Gregory Nutt
da0de3284e Fix errors in documentation and comments related to the Tickless OS. From Vijay Kumar 2014-08-09 06:41:38 -06:00
Gregory Nutt
e1769b22f1 Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures 2014-08-08 18:39:28 -06:00
Gregory Nutt
d798dd37a7 Replace os_internal.h with sched/sched.h in files that actually reference something in sched.h 2014-08-08 17:53:55 -06:00
Gregory Nutt
23a334c066 Move task control files from sched/ to sched/task 2014-08-08 16:44:08 -06:00
Gregory Nutt
d4b56eb3cc Move clock functions from sched/ to sched/clock 2014-08-08 14:43:02 -06:00
Gregory Nutt
85e8117062 Move interrupt dispatch logic from sched/ to sched/irq 2014-08-08 14:31:15 -06:00
Gregory Nutt
c9661ad5a7 Change all time conversions. Yech. New timer units in microseconds breaks all existing logic that used milliseconds in the conversions. Something likely got broken doing this, probably because I confused a MSEC2TICK conversion with a TICK2MSEC conversion. Also, the tickless OS no appears fully functional and passes the OS test on the simulator with no errors 2014-08-07 18:00:38 -06:00
Gregory Nutt
0aa7209765 Change CONFIG_MSEC_PER_TICK to CONFIG_USEC_PER_TICK. This gives more options for system timers in general, but more importantly, let's us realize higher resolution for the case of CONFIG_SCHED_TICKLESS=y -- of course, at the risk of some new interger overvflow problems 2014-08-07 13:42:47 -06:00
Gregory Nutt
520a51a3e1 Implements the tickless OS 2014-08-07 11:39:16 -06:00
Gregory Nutt
dc48bec019 Add support for a simulated interval timer support verification of the tickless OS. 2014-08-06 18:29:29 -06:00
Gregory Nutt
cc7cb0f031 Don't build in sched_processtimer.c if CONFIG_SCHED_TICKLESS is selected. 2014-08-06 18:27:10 -06:00
Gregory Nutt
0452b1555b if CONFIG_SCHED_TICKLESS is defined, then the global variable g_system_timer does not exist 2014-08-06 18:26:16 -06:00
Gregory Nutt
736d3c169a Rename up_timerinit() to up_timer_initailize(); Add prototypes for candidate interfaces for the tickless OS; Don't build existing timer initialization logic if CONFIG_SCHED_TICKLESS is defined. 2014-08-06 16:26:01 -06:00
Gregory Nutt
7b9c44101d SAMA5D3 HSMCI: TX DMA is again disabled 2014-08-05 07:07:39 -06:00
Gregory Nutt
159bcc255d SAMA5 PCK: Add Main clock as an option for the PCK clock source 2014-08-03 10:17:50 -06:00
Gregory Nutt
c75bf6d741 SAMA5 SSC: Verify that the requested bit width is supported. Correct some alignment tests that depend upon the data bit width. 2014-08-02 14:26:49 -06:00
Gregory Nutt
83dab03576 SAMA5 WM8904: Fix errors in programmable clock output configuration 2014-08-01 15:18:58 -06:00
Gregory Nutt
805a02965c SAMA5 SSC: Start Delay is now configurable 2014-08-01 14:10:37 -06:00
Gregory Nutt
50bd2ba46c SAMA5 SSC: Frame Synch Delay is now configurable 2014-08-01 12:25:31 -06:00
Gregory Nutt
0b4090df0d SAMA5D SSC: Needs to account for data offset in audio buffer. 2014-07-31 19:14:24 -06:00
Gregory Nutt
c657139b30 SAMA5D3X-EK: Add support for the WM8904 audio CODEC 2014-07-31 11:14:57 -06:00
Gregory Nutt
24af676c05 SAMA5: Changes needed for a clean SAMA5D3 build after all of the recent SAMA5D4 changes. 2014-07-31 11:09:56 -06:00
Gregory Nutt
276cc44878 SAMA5 HSMCI: e-enable TX DMA and verify that DMA writes to the SD card are functional. They are so now TX DMA is re-enabled in the driver. This might affect the SAMA5D3 platforms where the TX DMA problem was found. The SAMA4D3 and 4 use the same HSMCI driver. Much has change since then and it is not surprising that DMA is now functional. However, the has not be re-verified on the SAMA5D3 which has a different DMA controller. 2014-07-30 11:20:06 -06:00
Gregory Nutt
4df0fbec04 SAMA5D HSMCI: Fix a problem on card insertion/removal callback handling. Interrupts were being disable so that the callbacks occurred with interrupts disabled. This resulted in loss of some interrupts and some not-so-good behaviors. The solution is to perform all callbacks on the work thread unconditionally (2014-7-29). 2014-07-30 10:19:41 -06:00
Gregory Nutt
70be3bae16 SAMA5D HSMCI: Add method to do RX transfer without DMA. The 8-byte SCR transfer was failing silently with the DMA transfer, leaving the SD card in single bit mode 2014-07-29 21:13:28 -06:00
Gregory Nutt
2861636015 Cosmetic changes to comments 2014-07-29 07:17:01 -06:00
Gregory Nutt
53930d5531 SAMA5D-EK: Correct system timer frequency. Input clock is MCK/2, not MCK 2014-07-29 07:12:36 -06:00
Gregory Nutt
1b6eec572d Cosmetic changes to comments 2014-07-29 07:11:16 -06:00
Gregory Nutt
8c2b458d75 Fixes to last SAMA5 PMIC checkin 2014-07-28 17:09:37 -06:00
Gregory Nutt
d450993f2e LPC17xx: DC updates from Max. Also fixes some syntax errors that I introduced in the last commit. 2014-07-28 07:23:49 -06:00
Gregory Nutt
100bba42be ARM: Move L2 cache initialization to much later in the sequence 2014-07-27 10:03:33 -06:00
Gregory Nutt
c523abdc62 ARMv7-A L2 Cache currently depends on EXPERIMENTAL because it does not yet work properly 2014-07-26 18:48:54 -06:00
Gregory Nutt
4446d6e98d ARMv7 L2 Cache: Minor bugfixes/improvements 2014-07-26 18:48:26 -06:00
Gregory Nutt
0519118de2 Enables cache early in boot-up sequence 2014-07-26 18:48:00 -06:00
Gregory Nutt
d09ee81320 Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled 2014-07-26 18:47:33 -06:00
Gregory Nutt
0d83d198de New cache.h file. Renames cp15_XYZ_cache() to arch_XYZ_cache() and addes L2 cache support if L2 cache is enabled 2014-07-26 18:46:52 -06:00
Gregory Nutt
ca3776a7ec Rename ARMv7-A cache.h to cp15_cache.h. Things will be broken on this commit until I get the new cache.h in place. 2014-07-26 16:54:19 -06:00
Gregory Nutt
ec70cfe44c arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache. 2014-07-26 16:50:08 -06:00
Gregory Nutt
be198337f7 ARMv7-A: L2CC PL310 address filtering is an optional feature 2014-07-25 19:46:09 -06:00
Gregory Nutt
ef5bfd72a6 ARMv7-A: Add missing L2CC PL310 bit definitions 2014-07-25 19:41:35 -06:00
Gregory Nutt
597c9839cc rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well. 2014-07-25 17:25:17 -06:00
Gregory Nutt
47752a35c1 3rd time is a charm. Max is right, the initial priority setting should be NVIC_SYSH_PRIORITY_MIN 2014-07-24 16:51:07 -06:00
Gregory Nutt
8718dad9c8 Oops, should have been NVIC_SYSH_PRIORITY_DEFAULT 2014-07-24 16:42:15 -06:00
Gregory Nutt
7f5b88dbcd LPC17 Ethernet: Added option to use the kernel worker thread to do most of the workload with CONFIG_NET_WORKER_THREAD option in Kconfig. Eliminated a problem with PHY DP83848C : it doesn't need a specific initialization on mbed. Critical bufix: From time to time (after some hours) the Ethernet receiver would lose one receive interrupt and the IP stack never recover because there is no receive watchdog as the transmit watchdog. From Max 2014-07-24 16:39:18 -06:00
Gregory Nutt
fdff663e57 Added burstmode ADC conversion mode, with CONFIG_ADC_BURSTMODE option in Kconfig. From Max 2014-07-24 16:23:31 -06:00
Gregory Nutt
ab572091c5 Mostly cosmetic changes from Max 2014-07-24 16:00:21 -06:00
Gregory Nutt
ad3626e61a Eliminate warnings. From Max 2014-07-24 15:50:37 -06:00
Gregory Nutt
6dcb524d16 Correct the initial value of the BASEPRI register. This was apparently never being initialized. From Max 2014-07-24 15:37:13 -06:00
Gregory Nutt
0fcc0adaa2 Fix a recently introduced typo that was being masked by some bad conditional compilation 2014-07-22 11:45:14 -06:00
Gregory Nutt
17abe05357 Update ChangeLog 2014-07-22 07:25:01 -06:00
Gregory Nutt
3bb6a877fd STM32 OTGFS device: Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled. Needs verification on other platforms. From Petteri Aimonen 2014-07-22 07:23:17 -06:00
Gregory Nutt
f76cac2773 Fix typos in the STM32 DAC header file. From Petteri Aimonen 2014-07-22 07:13:33 -06:00
Gregory Nutt
121c00036d SAMA5D4 XDMAC: Never sets a channel as secure. Will probably have to revisit this 2014-07-21 17:46:35 -06:00
Gregory Nutt
df65c5e4df SAMA5D4: Fix some HSMCI issues when XDMAC0 is enabled 2014-07-21 17:45:48 -06:00
Gregory Nutt
b9f1fbeb6c SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC 2014-07-21 16:49:56 -06:00
Gregory Nutt
f508c07b97 SAMA5 XDMAC: Missing some CUBC bits 2014-07-21 16:47:16 -06:00