hartmannathan
bfc153ca27
Fix typos in comments and documentation ( #750 )
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* Fix typos in comments and documentation
2020-04-08 06:45:35 -06:00
Xiang Xiao
80277d1630
Refine the preprocessor conditional guard style ( #190 )
2020-01-31 19:07:39 +01:00
Björn Brandt
38b043da9f
arch/arm/src/stm32f7/: Apply fix introduced by 0947b31fbb for STM32F7[6/7]XX to STM32F7[2/3/4/5]XX.
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In RCC configuration, STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S; PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S
2020-01-08 07:11:59 -06:00
Ramtin Amin
7d2bd2371f
arch/arm/src/stm32f7: USB High speed for STM32F7 series
2019-04-07 19:05:06 -06:00
William Douglas
c708f66aea
Squashed commit of the following:
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commit 7fd1f0d78546fa0315f4077b779efdd884e5bd53
Author: William Douglas <william@rocklandscientific.com>
Date: Tue May 15 13:19:31 2018 -0700
Add support for the second SDMMC device.
The second SDMMC device was already supported but
the clock was never enabled. This fixes that.
2018-05-15 17:08:20 -06:00
Jussi Kivilinna
88cf9cf133
Two changes for STM32F7.
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1) The first enables building with CONFIG_ARCH_IDLE_CUSTOM enabled.
2) The second allows changing voltage output scaling setting and prevents enabling over-drive mode for low frequencies (STM32 F74xx, 75xx, 76xx, 77xx)
2017-11-21 06:42:04 -06:00
Jussi Kivilinna
449a891a8e
stm32f7: add new configuration option for enabling flash ART Accelerator and flash prefetcher
2017-09-04 07:56:51 -06:00
Titus von Boxberg
28eab902d0
No FSMC, only FMC for STM32F7
2017-07-27 18:27:01 +02:00
Gregory Nutt
9b11187b2a
STM32 OTG HS: A little research reveals that only the F2 RCC initialization set the OTGHSULPIEN bit and Photon is the only F2 board configuration that uses OTG . Therefore, we can simplify the conditional logic of the last PR. Negative logic was used (#ifndef BOARD_DISABLE_USBOTG_HSULPI) to prevent bad settings in other configurations. But give these facts, the preferred positive logic now makes more sense (#ifdef BOARD_ENABLE_USBOTG_HSULPI).
2017-03-11 18:00:38 -06:00
Gregory Nutt
e0f7b9582a
STM32: Review of last STM32 F2 PR. Progate changes to STM32 F4 and F7 OTGHS. Rename some configs/photon/src files. Naming can be either photon_ or stm32_ but must be consistent.
2017-03-11 16:31:11 -06:00
Jussi Kivilinna
dd1aa2357b
Allow board to configure HSE clock in bypass-mode. This is needed to enable HSE with Nucleo-F746ZG board.
2017-02-17 07:15:22 -06:00
Lok Tep
a2e4c0e898
i2s rcc typo fix
2016-10-07 15:12:34 +02:00
David Sidrane
a4040759b0
Adding PWR, RTC, BBSRAM for stm32f7
2016-06-27 16:42:01 -10:00
David Sidrane
8289e3eb7c
Updated F7 RCC to support all pll and config registers
2016-06-17 12:48:30 -10:00
Gregory Nutt
7dbfae87ec
STM32 F7: Correct some spacing issues
2015-10-07 13:58:11 -06:00
Gregory Nutt
12f04f8500
STM32 F7: Add heap initializatino logic; Clone the STM32 CCM allocator as the F7 DTCM allocator
2015-07-18 12:52:24 -06:00
Gregory Nutt
465d7fe8c5
STM32 F7: Add PWR register definitions
2015-07-18 11:55:35 -06:00
Gregory Nutt
9c78772fce
STM32 F7: Add RCC clock configuration logic from STM32 F429
2015-07-17 17:39:33 -06:00
