sergiotarxz/nuttx
sergiotarxz/nuttx
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19217 Commits

Author SHA1 Message Date
JacobCrabill
f406afdc42 arch/stm32h7: Add FDCAN SocketCAN driver 
Adds an FDCAN driver for STM32H7 MCUs using the SocketCAN interface
 2022-05-06 08:54:58 +02:00
Oki Minabe
4fa21c4719 armv7-a: Inner Shareable TLB maintenance operations 
Summary:
- Use Inner Shareable for TLB maintenance operations
- Add config option as CONFIG_ARM_HAVE_MPCORE
- This PR is in preparation for smp with kernel build

Impact:
- armv7-a

Testing:
- sabre-6quad:smp w/ qemu
- sabre-6quad:knsh_smp w/ qemu (WIP)

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
 2022-05-06 15:26:59 +09:00
Xiang Xiao
45fb96c508 esp32x/wlan: Fix error: increment of a boolean expression 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-05 16:23:32 -03:00
chao.an
0c223998c7 arm/cortex-m/toolchain: try print runtime library only in clang 
fix compile warning:

make: arm-nuttx-elf-gcc: Command not found

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-05-05 17:31:12 +02:00
Xiang Xiao
c1082f04d3 libxx: Make HAVE_CXXINITIALIZE workable even HAVE_CXX isn't enabled 
since this infrastructure is also used in no c++ case(e.g. gcov)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-04 08:58:43 +02:00
Abdelatif Guettouche
b19b931722 arch/xtensa/src/common/xtensa_coproc.S: Use the first allocated memory 
for the local variable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-05-04 01:39:07 +08:00
Simon Filgis
6e8c32e778 MCAN_INT_ACKE must be on the list of MCAN_TXERR_INTS to be properly handeled 2022-05-04 01:38:25 +08:00
Anton Potapov
862b815f87 Restore lost flash define for stm32. 2022-05-03 23:07:15 +08:00
Xiang Xiao
972a260391 arch/arm: Remove FAR and CODE from chip folder(3) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-03 16:50:52 +03:00
Xiang Xiao
44ad6d0a23 arch/arm: Remove FAR and CODE from chip folder(2) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-03 16:50:52 +03:00
Xiang Xiao
03c31d332f arch/arm: Remove FAR and CODE from chip folder(1) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-03 16:50:52 +03:00
Ville Juven
248b738f25 arm_addrenv: Add stubs for modifying permissions 
Adds stubs for up_addrenv_text_enable/disable_write. These don't have
to do anything as the ARM MMU allows setting access per mode. Currently
the settings for user .text area grants the kernel write access, but
revokes user write access.
 2022-05-03 21:25:25 +09:00
Ville Juven
9af8b740e6 Elf loader: give temporary write access to user .text memory 
When the .elf file is loaded from disk, the kernel must be given write
access to the allocated .text section in the task's address environment.

The access is removed after the elf is loaded and relocations are done.

NOTE:
The reason this works for the ARM implementation, is that the ARM MMU
can be configured to give write access for the privileged mode, but
revoke write access for the user mode.

Regardless, it would be smart to revoke write access even for the
kernel, when the kernel does not need it. This framework allows doing
that, if someone wishes to take up the task.
 2022-05-03 21:25:25 +09:00
Oki Minabe
0ba891c1b0 armv7-a: smp: fix stack coloration 
Summary:
- The stack pointer is subtracted to alloc xcptcontext area
  in the __cpu?_start block
- Fix the stack coloration overrun to the previous cpu's xcpt area

Impact:
- armv7-a's smp configuration

Testing:
- smp and ostest on sabre-6quad:smp w/ qemu

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
 2022-05-03 19:12:04 +08:00
Ville Juven
2fd29b6408 RISC-V: Fix bug in riscv_addrenv.c 
Need 1 full page extra for heap, not 1 byte.
 2022-05-03 03:05:22 +08:00
Masayuki Ishikawa
5a9b2920e8 arch: risc-v: Add support for semihosting and hostfs 
Summary:
- This commit adds support for semihosting and hostfs

Impact:
- None

Testing:
- Tested with nsh and nsh64 (defconfig will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-05-02 19:46:58 +08:00
Ville Juven
0ae2e68116 RISC-V: Temporarily disable error about missing SBI 2022-05-02 16:13:15 +08:00
Ville Juven
31b916c485 MPFS: Add kernel space mappings 
Mappings are done with vaddr=paddr.
- I/O space mapped with two gigapages
- Kernel space mapped to statically allocated page tables. 2MB of kernel
  memory is supported.
- Page pool is mapped to the kernel space, to allow virtual memory access
  for the kernel e.g. to initialize the page memory when it is allocated.
 2022-05-02 16:13:15 +08:00
Ville Juven
3f6504076e MPFS: Add page pool allocation 2022-05-02 16:13:15 +08:00
Ville Juven
cccfe31d0c MPFS: Add sources for CONFIG_ARCH_ADDRENV 2022-05-02 16:13:15 +08:00
Ville Juven
6bf8623897 RISC-V: Fix crt0 file compilation 
Definition of STACK_FRAME_SIZE was moved
 2022-05-02 16:10:47 +08:00
Xiang Xiao
f77a0ec7fa arch: Move -finstrument-functions from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 23:54:15 +03:00
Xiang Xiao
1fde7e17bb arch: Move -fstack-protector-all from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 23:54:15 +03:00
Xiang Xiao
aeb9c5d822 boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs 
and migrate MAXOPTIMIZATION into ARCHOPTIMIZATION

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:36:41 +03:00
Xiang Xiao
1e23799455 arch/riscv: Optimize the syscall performance in kernel mode 
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:31:01 +03:00
Xiang Xiao
efce8bd198 Revert "arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm" 
This reverts commit 9b7f9867aad7ff2d04b97516ab86b68d733447b6.
 2022-05-01 11:31:01 +03:00
Xiang Xiao
a021177de8 arch: Fix the style found in review 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-05-01 11:29:44 +03:00
chao.an
5db447623d arm/cxd56xx/lc823450/rp2040: replace arch testset to board implement 
This patch to resolve the regression which leads to the breakage of spresense:smp

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-05-01 06:38:25 +09:00
chao.an
3ec2f70046 arch/arm/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
8951b0135b arch/cortex-[a|r]/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
5677fe2153 arch/cortex-m/Make.defs: unify arch common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
chao.an
a560eb5f8d arch/arm/Make.defs: unify common source include 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-30 21:50:16 +08:00
Xiang Xiao
2a95be5086 arch/avr: Remvoe the error message when toolchain can't find 
to avoid blocking the basic ci check

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-30 01:20:11 -03:00
Xiang Xiao
94cb0c6072 arch: Move -nostdinc++ to Tooolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-29 21:08:14 -03:00
Simon Filgis
385519302e Corrected typo in sam_spi.c. Debaugcall needs cs not if as ref... 
Signed-off-by: Simon Filgis <simon@ingenieurbuero-filgis.de>
 2022-04-30 03:13:38 +08:00
Oki Minabe
c38234e342 armv7-a/r: use cps instruction to change cpu mode 
Summary:
- Use CPS instruction to change cpu mode for code simplification
- CPS which changes cpu mode is available in armv6 and above

Impact:
- armv7-a/r

Testing:
- smp and ostest on sabre-6quad:smp w/ qemu

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
 2022-04-30 03:13:22 +08:00
Ville Juven
b3baf95835 UMM: Implement getter for address environment heap start vaddr 
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.

Added stubs for ARM and Z80 also.
 2022-04-29 23:13:16 +08:00
Sergey Nikitenko
19c5ac9135 stm32l4 fix ECCR comment 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
3cc8d7d52a stm32l4 rtcc register fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
0b9a36d142 stm32l4 fix tim channel range checking 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
541b03b787 stm32l4 TIM register fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
57c64d327e stm32l4 FLASH_CR_FSTPG register fix 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
50fb3b5dc0 stm32l4 fixing proper register name RCC_APB1ENR1_PWREN 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
b73e89a674 stm32l4 RCC multi-bit field fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
7e4193c4a3 stm32l4 remove useless RTCPRE setup 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
9850766d07 stm32l4 RCC SW/SWS comment fixes 2022-04-29 09:30:09 +03:00
Sergey Nikitenko
3da7706db8 stm32l4+ DMAMUX register fix 2022-04-29 09:30:09 +03:00
Abdelatif Guettouche
da273fce0b arch/xtensa: Replace the xcp context with stack context to improve context switching 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-29 02:51:41 +08:00
Ville Juven
e674d5cb86 RISC-V: Add crt0 file 
Contains the code for the user process signal trampoline.
 2022-04-29 02:02:15 +08:00
Ville Juven
0ccda05a82 RISC-V: Move wipe_page to pgalloc.h and rename it riscv_pgwipe 2022-04-29 02:02:15 +08:00