Commit Graph

2909 Commits

Author SHA1 Message Date
Gregory Nutt
412aaa83a2 SAMA5D3x-EK: At support for the AT25 serial FLASH 2013-08-04 16:56:41 -06:00
Gregory Nutt
5fe6e4df26 SAMA5: Add register level debug option for SPI 2013-08-04 14:45:24 -06:00
Gregory Nutt
d516baa73f SAMA5: SPI driver now supports both SPI0 and SPI1 2013-08-04 12:50:20 -06:00
Gregory Nutt
487866b2b6 SAMA5: Add basic SPI suppport (untested) 2013-08-04 11:08:20 -06:00
Gregory Nutt
8194e6bbcf SAMA5: Add DMA suppport (untested) 2013-08-04 10:44:18 -06:00
Gregory Nutt
a93b095ce4 SAMA5: Add DMA controller register definitions 2013-08-03 12:13:42 -06:00
Gregory Nutt
8b317e9ea3 Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts 2013-08-03 08:22:37 -06:00
Gregory Nutt
c7293535fe Various changes to get SAMA5 SDRAM working. Marginally functional, but there is more to be done 2013-08-02 18:30:27 -06:00
Gregory Nutt
08a1ff5c79 Correct some typos int he MPADDRCS register address definitions 2013-08-02 12:06:11 -06:00
Gregory Nutt
b00d72a7f2 SAMA5: More MMU-related changes to properly initialize SDRAM 2013-08-02 11:11:57 -06:00
Gregory Nutt
894618f894 SAMA5: Add logic to initialize SAMA5D3x-EK on-board SDRAM 2013-08-01 16:58:55 -06:00
Gregory Nutt
70e1028d41 SAMA5: Add DDR controller register definitions 2013-08-01 12:27:41 -06:00
Gregory Nutt
35c3a49e1c ARMv7-A: Map all of .text, .bss, .data., stacks before enabling the MMU and caching. This is simpler and avoids fears I have about caching 2013-08-01 10:05:33 -06:00
Gregory Nutt
f0e6d4f101 ARMv7-A: Separate CONFIG_PAGING start-up logic into a different startup file. Too much conditional compilation. 2013-08-01 07:41:00 -06:00
Gregory Nutt
b0045bc7e2 SAMA5: Add an NSH configuration of the SAMA5D3x-EK board 2013-07-31 10:46:13 -06:00
Gregory Nutt
8695c89aa4 SAMA5: Modification of some CPSR-related inline functions 2013-07-31 09:11:24 -06:00
Gregory Nutt
db20c5fc43 Fix Cortex-A CPSR register field definition 2013-07-30 19:05:24 -06:00
Gregory Nutt
391d300d4d SAMA5: Change mapping of vector tables to work around that fact that I don't understand how the AXI MATRIX remap works 2013-07-30 16:19:52 -06:00
Gregory Nutt
16371b50e4 ARMv7-A: Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM 2013-07-30 13:20:33 -06:00
Gregory Nutt
6f99994722 More DAC changes from John Wharington 2013-07-30 11:41:53 -06:00
Gregory Nutt
b75a0cf8be Add ARMv7-A irqdisable() inline function 2013-07-30 11:37:09 -06:00
Gregory Nutt
84150fd7ed STM32 F3 I2C driver from John Wharington 2013-07-30 10:35:17 -06:00
Gregory Nutt
4bdcceb3b3 STM32 DAC DMA fixes from John Wharington 2013-07-30 08:54:32 -06:00
Gregory Nutt
547f9be80f SAMA5: More cache and mmu inline utility functions 2013-07-29 19:57:15 -06:00
Gregory Nutt
95998c715f SAMA5: Separate cache operations into separate files 2013-07-29 18:38:02 -06:00
Gregory Nutt
f658bcdb13 Changes to ARMv7-A boot logic to handle the case where we execute out of NOR FLASH 2013-07-29 17:54:56 -06:00
Gregory Nutt
4e90fae5e8 Add SAMA5 HSMC register definitions and logic to reconfigure the NOR FLASH 2013-07-29 10:56:21 -06:00
Gregory Nutt
27a9da98f4 SAMA5: Add file structure to support board-specific initialization of NOR flash 2013-07-29 07:41:53 -06:00
Gregory Nutt
65c8abddb8 SAMA5: The ostest configuration have been converted to run out of NOR flash. There is more to be done, however 2013-07-28 15:07:35 -06:00
Gregory Nutt
7dfabf3507 SAMA5: Correct a clock configuration bug; clarify some MMU memory types 2013-07-28 12:44:06 -06:00
Gregory Nutt
f191ac94c0 SAMA5: Correct vector mapping 2013-07-28 09:44:11 -06:00
Gregory Nutt
9a5311296f Removed unused ARMv7-A cache function 2013-07-27 14:03:02 -06:00
Gregory Nutt
ae6ed8ca52 SAMA5: Fix heap allocation bugs 2013-07-27 11:28:31 -06:00
Gregory Nutt
3d16c9afc7 SAMA5 page table is cached; need to flush the cache each time that the page table is updated 2013-07-27 09:27:37 -06:00
Gregory Nutt
87af1517ed Correct an error in Cortex-A5 intermediate MMU mapping 2013-07-26 17:26:53 -06:00
Gregory Nutt
14093ef76a Add a hello world configuration to help with the SAMA5 bringup 2013-07-26 15:28:01 -06:00
Gregory Nutt
2f772c84fd Finally... renamed all CONFIG_DRAM_ settings to CONFIG_RAM_ 2013-07-26 10:09:17 -06:00
Gregory Nutt
f87963accd SAMA5: If the page table is in high memory, make sure that it is excluded from the heap 2013-07-26 09:16:46 -06:00
Gregory Nutt
4ea9e1eb6e Fix some bad page table definitions of last commit 2013-07-25 18:11:25 -06:00
Gregory Nutt
696f6d0482 Misc Cortex-A5 MMU-related fix -- still does not boot 2013-07-25 16:37:55 -06:00
Gregory Nutt
d1be1e6698 Fix an uninitialized register error that crept into the ARM9 start up code many years ago and was recently cloned into the Cortex-A5. Obviously no on has used NuttX with ARM9 for years 2013-07-24 20:12:04 -06:00
Gregory Nutt
f337f3a977 Fix SAMA5 vector linking issue 2013-07-24 12:51:42 -06:00
Gregory Nutt
213780bc43 Update SAMA5D3x-EK board configuration to support on-board UART connections, LEDs, and push buttons 2013-07-24 12:27:12 -06:00
Gregory Nutt
63f136dd7e Revamp the way external memory regions are configured; Add logic to add SAMA5 external memory regions to the heap 2013-07-24 10:08:32 -06:00
Gregory Nutt
a81abd3514 Improve Cortex-A5 context switching so that a little less copying is done 2013-07-24 07:47:51 -06:00
Gregory Nutt
2e8fcc7229 ARMv7-N: Fix a copy error introduced in the previous check-in 2013-07-23 19:09:17 -06:00
Gregory Nutt
cb3f394d53 Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A 2013-07-23 17:52:06 -06:00
Gregory Nutt
9e24c4fcd5 ARMv7-A: Need 8-byte stack alignment when callign C code from interrupt handlers. This change needs to be ported to other ARM architectures as well 2013-07-23 14:47:16 -06:00
Gregory Nutt
596cdf2982 SAMA5: Adapt clocking for different boot modes. New header files for AXI matrix, BSC, and SFR 2013-07-23 13:54:49 -06:00
Gregory Nutt
ae3f2b2876 Add SAMA5D3 pin multiplexing definitions 2013-07-23 09:47:01 -06:00