Commit Graph

14907 Commits

Author SHA1 Message Date
David Sidrane
df4eb4896d s32k3xx:LPSPI register usage cleanup 2022-12-15 22:21:32 +08:00
Petro Karashchenko
949a0d6032 arch/arm: remove FAR from ARM files
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-12-15 11:38:17 +08:00
Peter van der Perk
d172d8cd0f S32K FlexCAN don't use a blocking wait in tx avail 2022-12-14 10:45:43 -05:00
David Sidrane
1760057e29 s32k1xx:Apply Style Changes from code review
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-12-14 21:03:31 +08:00
David Sidrane
592e946bdf 32k1xx:serial:Support GPIO (buffler level) Flow control 2022-12-14 21:03:31 +08:00
David Sidrane
5a948ed3dd 32k1xx:serial fix HW Handshaking 2022-12-14 21:03:31 +08:00
David Sidrane
9bb1226b04 s32k1xx:serial Add EDMA 2022-12-14 21:03:31 +08:00
David Sidrane
8a412ba59b s32k1xx:Refactor DMAMUX for s32k11x, s32k14x 2022-12-14 21:03:31 +08:00
anjiahao
bc0fe0ea16 crypto:add some hardware support
esp32c3: aes hmac-sha1 hmac-sha256
stm32f0l0g0 stm32l1 : aes
sam34: aes
lpc43: aes
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2022-12-14 02:33:56 +08:00
anjiahao
2b071b7a42 arch/armv8m:support pmu api
The register definition comes from CMSIS
https: //github.com/ARM-software/CMSIS_5
commit id:10bf763a82318c0c852ff9ecc2d5cd8cebe7d761
file: Core/Include/pmu_armv8.h
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2022-12-14 00:27:02 +08:00
David Sidrane
4284d0398b imxrt:Serial LPUART_STAT_PF s/b LPUART_STAT_NF
as a result of a typo LPUART_STAT_NF was not checked and
   cleared on LPUART_STAT_PF.
2022-12-14 00:26:42 +08:00
Peter van der Perk
6b3b5751c1 S32K automatically calculate size of periphclocks array 2022-12-13 19:50:01 +08:00
chao an
47fbfa215e fs/hostfs: mode_t of mkdir(2) should use the nuttx prototype
Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-13 18:16:20 +08:00
田昕
0382b63f5d move common assert logic together.
Signed-off-by: 田昕 <tianxin7@xiaomi.com>
2022-12-12 17:05:02 +08:00
zhangyuan21
ffd2eb5b14 arch/arm: only compare callee-saved registers for fpu
Registers S0-S15 (D0-D7, Q0-Q3) do not need to be preserved. They can be used for passing
arguments or returning results in standard procedure-call variants.
Registers D16-D31 (Q8-Q15), do not need to be preserved.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-09 11:00:38 +08:00
wangbowen6
27ea9f7625 arm/Kconfig: add cortex-m85 config
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-12-09 01:53:10 +08:00
wangbowen6
c44f87eb1a arm: add syscall SYS_save_context support for old arm and armv7-r
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-12-08 12:37:29 +08:00
TimJTi
18482efc39 SAMA5D2 fix printf formatter
Update sam_adc.c

Update sam_adc.c

%08x -> PRIx32

More %08x

Revert incorrect change (PRIx32)

Update sam_tc.c

Update sam_tc.c

more style corrections/typos

Update arch/arm/src/sama5/sam_adc.c

Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
2022-12-07 21:33:17 +01:00
Peter van der Perk
9c27d96b8a s32k3xx:LPSPI Check for TX complete before RX
Co-authored-by: David Sidrane <david.sidrane@nscdg.com>
2022-12-05 22:35:21 +08:00
Peter van der Perk
e7449cf97a S32K3XX EDMA Set Backdoor for DTCM memory map 2022-12-05 22:35:21 +08:00
chao an
d12ddf56df arm/arm: sync ARM_THUMB support from cortex-a
Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-05 01:09:31 +08:00
Xiang Xiao
c6e9edcbb6 net: Rename arp_arpin to arp_input
align with other similar function(e.g. ipv4_input and ipv6_input)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-04 20:39:21 +08:00
chao an
62004a28a6 net/d_buf: remove d_buf reference from l3/l4
l3/l4 stack will decouple the reference of d_buf gradually, Only legacy
devices still retain d_buf support, new net devices will use d_iob

Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-04 20:37:14 +08:00
chao an
4b70e4ff77 arm/cortex-r: sync ARM_THUMB support from cortex-a
Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-04 20:12:31 +08:00
wangbowen6
4859d40a51 arm_syscall: add SYS_save_context for armv7-a
I noticed that there is not register information in the crash log
when DEBUGASSERT failed, the reason is that the arm_dumpstate()
call up_saveusercontext() to get the context of current task but
armv7-a do not support syscall SYS_save_context.

crash log:
[48/12/ 7 16:14:03] [CPU1] [10] [a7] up_assert: Assertion failed CPU1 at file:mm_heap/mm_free.c line: 115 task: panel_apps
[48/12/ 7 16:14:03] [CPU1] [10] [a7] backtrace|10: 0x38443440 0x38081f30 0x38002888 0x3802cb7c 0x38036e34 0x38037978 0x380386f0 0x38037e64
[48/12/ 7 16:14:03] [CPU1] [10] [a7] backtrace|10: 0x38036edc 0x380376a0 0x38035a2c 0x380070d0 0x3804eae4 0x3802abd0 0x3802277c 0x3804b998
[48/12/ 7 16:14:03] [CPU1] [10] [a7] backtrace|10: 0x38091be8 0x38099250 0x38096adc 0x3808f134 0x3802d5d8 0x380191a4
[48/12/ 7 16:14:03] [CPU1] [10] [a7] arm_registerdump: R0: 00000000 R1: 00000000 R2: 00000000  R3: 00000000
[48/12/ 7 16:14:03] [CPU1] [10] [a7] arm_registerdump: R4: 00000000 R5: 00000000 R6: 00000000  R7: 00000000
[48/12/ 7 16:14:03] [CPU1] [10] [a7] arm_registerdump: R8: 00000000 SB: 00000000 SL: 00000000  FP: 00000000
[48/12/ 7 16:14:03] [CPU1] [10] [a7] arm_registerdump: IP: 00000000 SP: 00000000 LR: 00000000  PC: 00000000
[48/12/ 7 16:14:03] [CPU1] [10] [a7] arm_registerdump: CPSR: 00000000

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-12-04 01:52:49 +08:00
okayserh
0dafa5f921 Added initial USB support for stm32f746g discovery. 2022-12-03 20:06:47 +08:00
David Sidrane
da7fe760e8 s32k1xx:LPI2C Add DMA support
s32k3xx:LPI2C fix RESET so it compiles
2022-12-03 13:54:34 +08:00
David Sidrane
ddc178122e s32k3xx:EDMA Add Error handeling 2022-12-03 02:47:42 +08:00
David Sidrane
1d84656f79 s32k3xx:EDMA Add Looping and Cleanup 2022-12-03 02:47:42 +08:00
David Sidrane
22390df92d s32k3xx:EDMA fix DMAMUX1 access violation 2022-12-02 22:56:07 +08:00
chao an
c1c17794f9 arm/arm: generating assemble code in ARM states by default
The following changes omit the arm version:

| commit d321080351
| Author: chao an <anchao@xiaomi.com>
| Date:   Fri Dec 2 02:52:18 2022 +0800
|
|     arm/cortex-[a|r]: generating assemble code in ARM states by default
|
|     Signed-off-by: chao an <anchao@xiaomi.com>

Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-02 13:54:17 +08:00
TimJTi
b6c148e763 Style changes for sam_adc.c and sam_tsd.c 2022-12-02 01:09:25 +01:00
chao an
77aede7c87 arm/thumb: outputs an implicit IT block to avoid build break
Fix build break on thumb2 mode:
opus/celt/arm/celt_pitch_xcorr_arm-gnu.S: Assembler messages:
opus/celt/arm/celt_pitch_xcorr_arm-gnu.S:146: Error: thumb conditional instruction should be in IT block -- `movle pc,lr'

Reference:
https://developer.arm.com/documentation/100067/0612/armclang-Command-line-Options/-mimplicit-it

In A32 code, the integrated assembler accepts all conditional instructions
without giving an error or warning. In T32 code, the integrated assembler
outputs an implicit IT block when there is a conditional instruction
without an enclosing IT block. The integrated assembler does not give an
error or warning about this.

Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-01 22:14:34 +01:00
chao an
9ab97df0a5 arm/cortex-[a|r]/thumb: force assembler files to be interpreted as Thumb code
The option '-mthumb' is only valid for C source files and it is not passed to the assembler.

If 'thumb' is not considered in some assembly projects, the system will generate
'undefined instructions' when running incompatible instruction:

arm_undefinedinsn: Undefined instruction at 0x380cfc98

This assembly file should be compiled with .thumb but it doesn't:

380cfc90 <hobot_i8_i32_gemm_nn_m4_n8_neon>:
380cfc90: e92d4ff0  push  {r4, r5, r6, r7, r8, r9, sl, fp, lr}
380cfc94: ed2d8b10  vpush {d8-d15}
380cfc98: e59d4064  ldr r4, [sp, #100]  ; 0x64   <-- Undefined instruction
380cfc9c: e59d5068  ldr r5, [sp, #104]  ; 0x68
380cfca0: e59d606c  ldr r6, [sp, #108]  ; 0x6c
380cfca4: e59d7070  ldr r7, [sp, #112]  ; 0x70
380cfca8: e1a08120  lsr r8, r0, #2
380cfcac: e1a091a1  lsr r9, r1, #3
380cfcb0: e1a0a122  lsr sl, r2, #2

After enable thumb:
  .syntax unified
  .thumb
or
  -Wa,-mthumb

.Lhobot_i8_i32_gemm_nn_m4_n8_neon:
38001100: e92d 4ff0   stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
38001104: ed2d 8b10   vpush {d8-d15}
38001108: 9c19        ldr r4, [sp, #100]  ; 0x64
3800110a: 9d1a        ldr r5, [sp, #104]  ; 0x68
3800110c: 9e1b        ldr r6, [sp, #108]  ; 0x6c
3800110e: 9f1c        ldr r7, [sp, #112]  ; 0x70
38001110: ea4f 0890   mov.w r8, r0, lsr #2
38001114: ea4f 09d1   mov.w r9, r1, lsr #3
38001118: ea4f 0a92   mov.w sl, r2, lsr #2

This commit will enable the thumb option of the assembly file by default,
so that when compiling the assembly file, the machine code and the system will be in a consistent state.

----------------------------------------------------------------
https://gcc.gnu.org/onlinedocs/gcc-4.5.2/gcc/ARM-Options.html

GCC Manual:
-mthumb
  Generate code for the Thumb instruction set. The default is to use the 32-bit ARM
  instruction set. This option automatically enables either 16-bit Thumb-1 or mixed 16/32-bit
  Thumb-2 instructions based on the -mcpu=name and -march=name options.

  ** This option is not passed to the assembler. **
  ** If you want to force assembler files to be interpreted as Thumb code,
     either add a `.thumb' directive to the source or pass the -mthumb option
     directly to the assembler by prefixing it with -Wa. **

Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-01 22:14:34 +01:00
chao an
d321080351 arm/cortex-[a|r]: generating assemble code in ARM states by default
Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-01 22:14:34 +01:00
Peter van der Perk
90472785d3 S32K3XX QSPI No need to check TX FIFO buffer when MPU is correctly configured 2022-12-01 08:00:32 -05:00
Peter van der Perk
ec5030ebe6 S32K3XX RAM fixes MPU Dcache ECC 2022-12-01 08:00:32 -05:00
chao an
12b0fa9ec3 arm/sama5: fix recursive dependency
arch/arm/src/sama5/Kconfig:819:error: recursive dependency detected!
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/src/sama5/Kconfig:819:	choice <choice> contains symbol SAMA5_FLEXCOM0_USART
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/src/sama5/Kconfig:824:	symbol SAMA5_FLEXCOM0_USART is part of choice SAMA5_FLEXCOM0_USART
For a resolution refer to Documentation/kbuild/kconfig-language.txt
subsection "Kconfig recursive dependency limitations"
arch/arm/src/sama5/Kconfig:824:	symbol SAMA5_FLEXCOM0_USART is part of choice <choice>

Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-01 09:45:09 +08:00
TimJTi
a634da9a30 Fix SAMA5D2 ADC and TSD problems
SAMA5Dx ADC and TSD fixes

Ensures ADC and TSD work together. TSD now works on SAMA5D2 and should be OK, still, for other SAMA5D familiy members

Fix CI error

checkpatch error

Update arch/arm/src/sama5/sam_tsd.h

Squash commits to arch/arm/src/sama5/hardware/sam_adc.h

Update arch/arm/src/sama5/hardware/sam_adc.h

Update arch/arm/src/sama5/hardware/sam_adc.h

Update arch/arm/src/sama5/hardware/sam_adc.h

Update arch/arm/src/sama5/hardware/sam_adc.h

Update arch/arm/src/sama5/hardware/sam_adc.h

Update arch/arm/src/sama5/hardware/sam_adc.h

Update arch/arm/src/sama5/hardware/sam_adc.h

Squash commits to arch/arm/src/sama5/sam_tsd.c

Update arch/arm/src/sama5/sam_tsd.c

Update arch/arm/src/sama5/sam_tsd.c

Update arch/arm/src/sama5/sam_tsd.c

Update sam_tsd.c

Fixes after feedback from PR and additional testing

Update sam_tc.c

checkpatch.sh error was missed when fixing someone else's error...

feedback corrections missed

Co-Authored-By: Xiang Xiao <xiaoxiang781216@gmail.com>
Co-Authored-By: Petro Karashchenko <petro.karashchenko@gmail.com>

squashed everything after 248072e02C
2022-12-01 01:51:12 +08:00
TimJTi
57a21fbe1a Fixes for SAMA5D2 Flexcom USART
squashed everything after 8f8b8f5e05

Update Kconfig

Update Kconfig
2022-11-30 23:14:17 +08:00
ligd
b71f124b7b armv7-r: correct the wrong usage of ARMV7A_XX marco
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-11-28 12:21:32 +01:00
TimJTi
578f7783c6 Corrects PIO errors and omissions for SAMA5D2
Changes and corrections after review

Correct slow clock config
2022-11-28 16:37:44 +08:00
Xiang Xiao
6d30726a1b Remove the unnecessary "return;" at the end of function
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-11-27 22:23:50 +01:00
chao an
6fa60627eb net/devif/ip: build l2 header on the IP layer
Signed-off-by: chao an <anchao@xiaomi.com>
2022-11-27 12:13:45 +08:00
chao an
8850dee746 net/devif: move preprocess of txpoll into common code
Signed-off-by: chao an <anchao@xiaomi.com>
2022-11-27 12:11:12 +08:00
Nathan Hartman
03802dad13 NuttX graduated the Incubator; update repository links 2022-11-26 11:58:15 -08:00
Ville Juven
52228fd222 stm32f7: Fix compliation of stm32_flash.c (add stm32_waste.c)
/arch/arm/src/libarch.a(stm32_flash.o): in function `up_progmem_write':
/arch/arm/src/chip/stm32_flash.c:419: undefined reference to `stm32_waste'

Seems like the symbol definition + declaration were completely missing
2022-11-23 20:30:26 +08:00
Ville Juven
321b9ea732 stm32f7/stm32_bbsram.c: Fix build error due to changed include path
Use correct path to include mutex.h

Fixes:

chip/stm32_bbsram.c:42:10: fatal error: mutex.h: No such file or directory
   42 | #include <mutex.h>
      |          ^~~~~~~~~
2022-11-23 18:20:29 +08:00
Xiang Xiao
04f887b56d Fix Error: chip/stm32_eth.c:1892:7: error: variable 'i' set but not used
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-11-23 07:27:48 +01:00
chao an
f23ec0f995 Revert "tools/ci/arm/llvm/clang: bump up LLVMEmbeddedToolchainForArm to release-15.0.2"
This reverts commit b4bab51e86.

Issue:
Builtin math symbols are missing on llvm 15.0.2(libm.a):
https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/issues/158

Signed-off-by: chao an <anchao@xiaomi.com>
2022-11-22 07:43:02 -08:00