Summary:
- Since the stack coloration is done for every 32bits
this function should be done in the same way.
Impact:
- None
Testing:
- Tested with qemu-a53:nsh
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
N/A
Summary:
Arm64 support for NuttX, Features supported:
1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
qemu virt machine.
2. qemu-a53 board configuration support: it's only for evaluate propose
3. FPU support for armv8-a: FPU context switching at NEON/floating-point
TRAP is supported.
4. psci interface, armv8 cache operation(data cache) and smccc support.
5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko
Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail
Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:
https://bugs.linaro.org/show_bug.cgi?id=5825
it's seem GCC give a wrong instruction at certain machine which
without architecture features
the new toolchain is not available still, so just disable the MACOS
cibuild check at present
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
1. Fix error recovery mechanism during transmission error
handling (enable transmission at the end).
2. Fix compilation / operation with CONFIG_SAMV7_EMAC_PREALLOCATE=y
3. Enable fully configured address space for transmission queues
to allow sending packets with length more than 976 bytes. With
partially configured address space the AHB error is generated
during transmission of long packets.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
With faster data transfer rates, it was seen that the read
requests occasionally were issued while the USB RX operation
was actually in progress. This patch makes sure the system
doesn't accidentally read the RX fifo while it's being filled
up, but rather, checks for the RXCSRL_REG_EPN_RX_PKT_RDY_MASK
flag. This flag indicates the packet is ready to be read.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
cache_dbus_mmu_set and cache_ibus_mmu_set return positive values in case
of errors, so DEBUVERIFY could never detect them since this macro checks
for negative values.
Besides, the successful execution of those functions is mandatory for
the reliable operation under Protected Mode, so the verification is
always performed, even when DEBUG is not enabled.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
forget to update in this patch:
commit b02db04e00
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Sun Jun 5 17:10:19 2022 +0800
arch/assert: Keep the thread dump column order same as ps
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1.Move __XSTR from include/arch.h to include/irq.h
2.Move FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
* arch/arm/src/tiva/common/tiva_lowputc.c
(tiva_lowsetup):
For each UART, if Kconfig enables RTS/CTS (e.g.,
CONFIG_UART0_IFLOWCONTROL and/or CONFIG_UART0_OFLOWCONTROL),
configure the corresponding GPIO(s).
* arch/arm/src/tiva/common/tiva_serial.c:
(struct up_dev_s):
If CONFIG_SERIAL_IFLOWCONTROL, add a bool field 'iflow'. If
CONFIG_SERIAL_OFLOWCONTROL, add a bool field 'oflow'. This is
inspired by the implementation for kinetis.
(g_uart0priv, g_uart1priv, g_uart2priv, g_uart3priv, g_uart4priv,
g_uart5priv, g_uart6priv, g_uart7priv):
If Kconfig enables RTS/CTS for a UART (e.g.,
CONFIG_UART0_IFLOWCONTROL thru CONFIG_UART7_OFLOWCONTROL), set
the corresponding iflow and/or oflow flag(s).
(up_setup):
Check the above-mentioned iflow and oflow flags and set or unset
the RTSEN and/or CTSEN bits in the UART's CTL register to enable
the feature.
The "p" format specifier already prepends the pointer address with "0x"
when printing.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Sync driver interfaces, also fixes the handling of special pin value for
esp32s2_gpio_matrix_in and esp32s2_gpio_matrix_out functions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Starting the rptun with the autostart flag set will cause significant
delays at the boot, as it will wait for the master to be up. U-boot/linux
combination may take more than 10 seconds to boot to the point where the
rpmsg bus is initialized.
For now, the user needs to initialize the rptun separately, for example,
by issuing the following command:
rptun start /dev/rptun/mpfs-ihc
This command will also block if started before the rpmsg bus master is up.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
SAMA5D2 and SAMA5D4 does not support external reset.
Some SAMA5 board's Kconfig contain item SAMA5_SYSTEMRESET, but it is better in arch/arm/src/Kconfig.
Add a function to easily enable event handling on fabric and mss gpios. This
is similar to what exists e.g. for stm32 arm chips.
Also fix some small bugs in mpfs_configgpio related to IRQ bits configuration
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This patch fixes the following issues:
1. MPFS_EMMCSD_HRS06_EMM bitmask had to be 0x7, not 0x03
2. putreg32() caused outright memory corruption as the
arguments were in wrong order
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
When using HSE to clock RTC NuttX internal time is gaining 5.5 second per
minute. Problem was NuttX using 7182 for one of the RTC division factors,
it should have been 7812. The incorrect factors used are 7182 and 0xff.
These are used in 3-4 places within Nuttx and other places as 7812 and 0xff.
However, the STMicro app note AN4759 suggests using 7999 and 124, which is
what I've used.
Explanation: These 2 factors are used to divide the HSE clock (which at this
point is 1 MHz) to 1 Hz for the RTC hardware.
To test the 2 factors, add 1 to both numbers and multiply them together.
The result needs to be as close as possible to 1 MHz.
The suggested values of 7999 and 124 => 8000*125 = 1,000,000, the prime
factors. So, the best fix for Nuttx would be these values.
Issue discovered and fixed by Peter Moody
In order to support multiple LCD instances per board, add a pointer from
lcd_planeinfo_s to the lcd_dev_s which it belongs to. Also enhance the
putrun, getrun, putarea and getarea methods to pass through the
lcd_dev_s pointer to the respective device driver.
Port all LCD device drivers to this lcd_planeinfo_s extension.
Enhance SSD1306 driver to support multiple LCDs.
Signed-off-by: Michael Jung <michael.jung@secore.ly>
The old implementation needed a contiguous memory block for user
ROM/RAM. This is because there was only 1 L3 page table which can only
map a contiguous memory area.
Also, remove the PMP configuration which just complicates things,
rely on the MMU mappings instead.
Update PLL configuration parameters to match the values provided
by the vendor.
Also remove extra call to mpfs_pll_config() as it's already called
at mpfs_clockconfig().
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This patch adds corrected implementation of FLASH memory to be used
with progmem driver for use with mtd filesystems like nxffs or smartfs.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Summary:
- I noticed that QEMU shows a high CPU load.
- This commit re-adds imx_idle.c to avoid this issue.
Impact:
- None
Testing:
- Tested with sabre-6quad:smp with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This patch implements working support for EXTI GPIO.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
--
v1 -> v2:
Suggested by: Petro Karashchenko
- change (1 << n) to (1 << (n)) in macro definition
- change 1 << X to (1 << X) in code
- fix alignment
v2 -> v3:
Suggested by: Petro Karashchenko
- I was supposed to change (1 << pin) to 1 << pin, not the other way around:)
Summary:
- I noticed that sometimes uart shows nothing on the maix-bit board.
- This commit adds a workaround to avoid such the issue
Impact:
- k210 only
Testing:
- Tested with maix-bit
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This provides USB composite (CDC/ACM and Mass Storage) support
for mpfs board. In addition, a number of USB fixes are included:
- Support for Setup Out packets
- Proper support for larger than packet size writes
- Finishing setup packets properly
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Output "X" with showprogress and make a system reset.
Silently ignoring failed training is dangerous and will cause random behaviour if DDR is used
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
