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18735 Commits

Author SHA1 Message Date
zhuyanlin
f5d180bbdf xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO 
For up_irq_disable, use XCHAL_EXCM_LEVEL
For up_irq_save,  use XCHAL_IRQ_LEVEL.
Then we can use svcall in enter_crritical_section.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-25 20:43:03 +08:00
Huang Qi
e8552156b6 arch/risc-v: Remove unneeded ISA specifc interface 
They are not really defined and used in any where:
uint32_t up_getmisa(void);
uint32_t up_getarchid(void);
uint32_t up_getimpid(void);
uint32_t up_getvendorid(void);
uint32_t up_gethartid(void);

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-25 20:36:16 +08:00
Huang Qi
cfed970633 arch/misoc: Correct gurad macro for irq.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-25 20:36:16 +08:00
Huang Qi
8b66280b4f arch/risc-v: Update outdated comments 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-25 20:36:16 +08:00
Gustavo Henrique Nihei
ea1b49119a xtensa/esp32s3: Apply minor fixes to documentation and code style 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 10:51:25 +08:00
Gustavo Henrique Nihei
add99fead3 xtensa/esp32s3: Add support for Oneshot timer 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 10:51:25 +08:00
Masayuki Ishikawa
de95a8550f arch, board: Add thumb support to i.MX6 
Summary:
- This commit adds thumb support to i.MX6
- Also, applies the same coding style to arch_elf.c

Impact:
- i.MX6 only

Testing:
- Tested with sabre-6quad:smp (QEMU, Dev board)
- Tested with sabre-6quad:netnsh (QEMU)
- Tested with sabre-6quad:netknsh (QEMU, not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-02-25 10:51:12 +08:00
Xiang Xiao
25213c42a5 arch/arm: Remove the empty spinlock.h file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-25 09:18:53 +09:00
Abdelatif Guettouche
dc130b4830 arch/xtensa/esp32s2_irq.c: Correctly enable the software interrupt. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-02-25 08:55:41 +09:00
Gustavo Henrique Nihei
b49ee3d4ed xtensa/esp32s3: Add support for Main System Watchdog Timers 
Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 02:13:00 +08:00
Anton Potapov
9603b8f67c Add DAC2 configuration for stm32f405. 2022-02-24 12:09:41 -05:00
Gustavo Henrique Nihei
3400b42a33 xtensa/esp32: Fix a minor typo in documentation 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-24 17:43:39 +01:00
Gustavo Henrique Nihei
a5024a707d xtensa/esp32s3: Use the running CPU ID for enabling internal interrupts 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-24 17:43:39 +01:00
Gustavo Henrique Nihei
83f3ba6d22 xtensa/esp32s3: Add support for Timer Groups 0 and 1 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 00:13:34 +08:00
zhuyanlin
7d350204f0 xtensa: fix XTHAL_REL_LE not find 
fix `XTHAL_REL_LE` not find build break

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-24 22:13:46 +08:00
Xiang Xiao
6fa5885d2d arch/esp32: Update esp-wireless-drivers-3rdparty to verion 45701c0 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-24 09:05:40 +01:00
zhuyanlin
fc9791c269 xtensa:esp32s3: setup software interrupt as swi interrupt. 
Enable and setup software interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-24 00:06:43 +01:00
zhuyanlin
bf40d70df9 xtensa:esp32s2: setup software interrupt as swi interrupt 
Enable and setup software interrupt for esp32s2

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-24 00:06:43 +01:00
zhuyanlin
7b32ce190e xtensa:esp32: setup software interrupt. (bit 29) 
Enable and setup software interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-24 00:06:43 +01:00
Xiang Xiao
d7fe0127b0 Replece clock_gettime(CLOCK_REALTIME) with clock_systime_timespec if suitable 
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-24 01:06:36 +08:00
Xiang Xiao
43f57240e0 Replece clock_gettime(CLOCK_MONOTONIC) with clock_systime_timespec 
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-24 01:06:36 +08:00
chao.an
13889ba868 arch/arm: unify some duplicate code to common layer 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 21:35:55 +08:00
chao.an
6cc0aaf5b9 arch/arm: unify switch context from software interrupt 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 15:04:29 +09:00
chao.an
db3a40ac25 arch/armv7-r: unify switch context from software interrupt 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 15:04:29 +09:00
chao.an
61cd9dfca1 arch/armv7-a: unify switch context from software interrupt 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 15:04:29 +09:00
Gregory Nutt
1ded8bbabb Garbage configuration setting in EFM32 code 
arch/arm/src/efm32/efm32_start.c:

      /* For the case of the separate user-/kernel-space build, perform whatever
       * platform specific initialization of the user memory is required.
      * Normally this just means initializing the user space .data and .bss
       * segments.
       */

    #ifdef CONFIG_NUTTX_KERNEL
      efm32_userspace();
      showprogress('E');
    #endif

But there is no CONFIG_NUTTX_KERNEL configuration setting.  Comparing this to other architectures it is clear this should be

    #ifdef CONFIG_BUILD_PROTECTED
 2022-02-23 03:40:44 +08:00
Xiang Xiao
f1ed349dd9 sched/clock: Remove CLOCK_MONOTONIC option from Kconfig 
here is the reason:
1.clock_systime_timespec(core function) always exist regardless the setting
2.CLOCK_MONOTONIC is a foundamental clock type required by many places

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-23 01:21:26 +08:00
zhuyanlin
7b00c8bdb8 arch:xtensa: modify svcall to swint 
Reason: xtensa svcall only have level-1 interrupt level.
Sush do not generate interrupt when up_irq_save.
Software int can generate interrupt when up_irq_save.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-22 14:06:24 -03:00
chao.an
0aa0022b12 arch/armv7-a: replace SYS_signal_handler_return hardcode 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-22 17:59:02 +08:00
chao.an
e0fabbfdd6 arch/arm: replace SYS_syscall_return hardcode from syscall 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-22 17:59:02 +08:00
Xiang Xiao
2f24d2c265 arch/ceva: Replace OUTDIR with TOPDIR 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-21 09:25:26 +01:00
Xiang Xiao
163fe4ff0b boards: Replace CONFIG_CYGWIN_WINTOOL with CONVERT_PATH 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 21:15:36 +01:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 20:10:14 +01:00
Oki Minabe
e9a94a003d old arm: add BUILD_KERNEL code in arm/arm_vectors.S 2022-02-20 21:03:54 +09:00
Oki Minabe
19e5c8f6d3 armv7-a/r: fix SVC's sp restore in arm_vectors.S 2022-02-20 18:39:30 +08:00
Xiang Xiao
d29f3bd21c arm/rtl8720c: Remove the unused Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 04:15:34 +01:00
Huang Qi
da25883c64 arch/sim: Fix usrsock build break on macOS 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-18 09:06:46 -03:00
chao.an
5da5ffb7d4 sim/usrsock: correct the xid type to uint64_t 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-18 08:16:17 +01:00
Abdelatif Guettouche
ab18b7b3d3 esp32xx_irq.c: Fix CPU interrupt documentation to remove the MAC 
interrupt from the internal interrupt table.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
ee88235d81 esp32_irq.c: Don't reserve BT and Wifi CPU interrupts for APP CPU as 
they are attached to the PRO CPU.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
17e43b0b4a esp32_irq.c: For internal interrupts use the current CPU to enable them. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
3d2771c49a esp32_irq.c: Move interrupt initialisation for special drivers to 
`up_irqinitialize`.  `esp32_cpuint_initialize` is not a good place as
it's also called from CPU1.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-02-18 13:40:21 +08:00
Huang Qi
0c5aff9be6 risc-v/qemu-rv: Supports SMP up to 8 cores 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-18 13:25:01 +08:00
Huang Qi
36ff081b1a risc-v: Support more than 2 cores in riscv_cpu_boot 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-18 13:25:01 +08:00
Huang Qi
7c18290331 risc-v: Rename up_fault to riscv_fault 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-18 13:25:01 +08:00
lp.xiao
bc12260540 dp83848c ethernet phy interrupt support 2022-02-17 08:00:53 +01:00
Xiang Xiao
69a6072946 arch/ceva: Replace adj_stack_ptr with stack_base_ptr 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-17 11:06:09 +09:00
Xiang Xiao
814cab1cd1 arch/ceva: Mark the allocated stack with TCB_FLAG_FREE_STACK 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-17 11:06:09 +09:00
Xiang Xiao
f8df491d5d arch/ceva: Update tls handle to the latest mainline 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-17 11:06:09 +09:00
Xiang Xiao
4bc5b246ac arch/ceva: Remove B2C and C2B 
since TL420 doesn't support anymore, we
can safely remove the special hack for it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-17 11:06:09 +09:00