This is preparation for moving address environments out of the group
structure into the tcb.
Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
This is fixed by making a stack frame to the user stack and copying it
there.
- If the signal handler uses a system call, the kernel stack was completely
and unconditionally destroyed, resulting in a crash in the user application
There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
The value printed by assert() cannot always be trusted to be correct,
as it relies on the stack / stack pointer not being corrupt.
The CPU register always points to the faulting instruction so print it
out in the exception handler.
MCUboot support is no longer behind EXPERIMENTAL for the following
chips:
- ESP32
- ESP32-S2
- ESP32-S3
- ESP32-C3
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Allow bootloader to select run-time whether the payload binary is booted with
SBI or directly by jumping to entrypoint address.
- Use just one bitmask to select sbi or direct boot for each hart
- Add mpfs_set_use_sbi function to allow selecting how to boot
- Initialize the bitmask by default according to the configuration flags
- Add a header file for including the function prototypes in bootloader code
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
SHM area is just mapped memory, the physical backup is not owned by the
process, so the process must not free it.
In ARM this is already handled as the regions are destroyed one by one,
while this implementation does a page directory walk instead.
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.
Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
which is made by:
commit 87a1f69a3c
Author: Alan Carvalho de Assis <acassis@gmail.com>
Date: Fri Dec 16 15:23:39 2022 -0300
Modify the IRQ APIs to be compatible with ESP32/S2/S3
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- I noticed that rv-virt:ksmp64 sometimes stops during boot.
- Finally, I found that it posts the Supervisor Software Interrupt
before the OS finishes hardware initialization.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
"aes_cypher" is a function from NuttX crypto, so better use instead of
defining a new interface in the driver.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Summary:
- I noticed that mtimer stops around 30min after boot.
- Finally, I found that nesc overflows in riscv_mtimer_current().
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with rv-virt:nsh on QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
add the task from the specified task list to reduce time consuming.
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
delete the task from the specified task list to reduce time consuming.
After commit b7d2b38, the system suffers from -Warray-bounds warning with -Wall:
chip/mpfs_opensbi.c: In function 'mpfs_hart_to_scratch':
chip/mpfs_opensbi.c:251:26: warning: array subscript hartid is outside array bounds of 'sbi_scratch_holder_t[0]' {aka 'struct sbi_scratch_holder_s[]'} [-Warray-bounds]
251 | return (unsigned long)(&g_scratches[hartid].scratch);
Fix it by reverting back to what is was earlier. g_scratches shouldn't be in the bss
region that would be zeroed out.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
After the commit b8b541f, the system would not start up properly
with certain coldboot conditions. For example, if the OpenSBI picked
hart4 as the coldboot hart in preference to hart3, the system would
get stuck due to stack corruption. OpenSBI uses a lottery mechanism
to pick the coldboot hart.
Also fix g_scratches area in such a manner than it will not get
initialized to zero. If several harts initialize the area to zero, there's
danger the stack pointer gets wiped out.
Now any coldboot hart works.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
In the past, header file paths were generated by the incdir command
Now they are generated by concatenating environment variables
In this way, when executing makefile, no shell command will be executed,
it will improve the speed of executing makfile
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Currently the IHC (Inter Hart Communication) depends on OpenAMP and
rptun. However, the bootloader portion of the IHC doesn't need
either of them. Now they are wasting a lot of bootloader space.
Reorganize the bootloader portion into a separate file 'mpfs_ihc_sbi.c'.
This file contains the OpenSBI vendor extensions, or the only required
functionalities for the bootloader. On the other hand, 'mpfs_ihc.c'
contains the non-bootloader code.
This patch also makes it possible to utilize 2 RPMSG channels. This
has been tested so that 2 separate NuttXs on harts 1 and 2 communicate
with Linux kernel that runs on harts 3 and 4.
New configuration files are added as well:
- rpmsg-ch1: sample config for RPMSG
- rpmsg-ch2: sample config for another RPMSG channel
- rpmsg-sbi: sample bootloader config for RPMSG/OpenSBI
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This reverts commit ea9144bda8.
The commit made Icicle MPFS DDR useless. Revert the change for now.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
- Reduce "SPI Flash configuration" menu dependency on SPI Flash driver
just to MTD-related configs.
- Move SPI Flash Mode and Frequency configs to SPI Flash configuration
menu.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Make a separate config flag for enabling L2 cache. This is on by
default when compiling a standalone/bootloader configuration, but
can also be disabled for special cases, such as memory testing
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Summary:
- This commit refactors the entry point name for BUILD_KERNEL
to avoid misunderstanding the name
Impact:
- None
Testing:
- Tested with rv-virt:ksmp64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that the OS timer sometimes proceeds fast when
a task is scheduled to run on CPUO via IPI.
- Actually, qemu-rv implementation shares supervisor software
interrupt for both timer and IPI on CPU0.
- This commit fixes this issue.
Impact:
- qemu-rv only
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds SMP support for BUILD_KERNEL
Impact:
- RISC-V: BUILD_KERNEL + SMP only
Testing:
- Tested with rv-virt:ksmp64 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Run-time check for L3 page table size, to ensure it is large enough
to map all of the kernel memory.
NOTE: The check has to be run-time, as KFLASH_SIZE/KSRAM_SIZE are really
linker relocation symbols, and thus cannot be utilized compile-time.
L3 table maps 2MB of memory, this brings an implicit requirement for
any L3 region to be aligned to 2MB. This commit adds build time sanity
checks to ensure this requirement is met.
For other SvXX architectures the boundary requirement (might be) is
different.
Summary:
- This commit introduces g_percpu_spin to avoid deadlock
in riscv_percpu.c instead of using the global spinlock.
Impact:
- None
Testing:
- Tested with rv-virt:knsh64 and rv-virt:ksmp64 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
