Gregory Nutt 075b66d4bb Eliminate a warning		2015-09-01 13:35:38 -06:00
..
chip	SAMV7 QSPI: Use of CPHA in mode settings was inverted	2015-08-31 10:05:41 -06:00
chip.h
Kconfig	SAMV7 QSPI: Delays need to be in units of nsec, not usec. Default delays should be 0 nsec	2015-09-01 11:16:09 -06:00
Make.defs	arch/arm/src/up_iternal.h and several ARM Make.defs files: In the original implementation, NOT defined(CONFIG_ARMV7M_CMNVECTOR) was a sufficient test to determine if lazy floating point register saving was being used. But recents changes added common lazy register as well so now that test must be (NOT defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU)).	2015-08-31 08:40:02 -06:00
sam_allocateheap.c
sam_clockconfig.c	SAMV7 USBHS DCD: Add logic to detect high speed mode; use DEBUGASSERT to check input parameters	2015-08-22 08:58:38 -06:00
sam_clockconfig.h	SAMV7 USB: USB must be enabled before PMC 480MHz clock is enabled	2015-08-11 15:48:26 -06:00
sam_config.h	SAMV7 SPI Slave: Add a basic driver framework for SPI slave. Still a lot of missing logic	2015-08-09 12:04:43 -06:00
sam_emac.c	Update some comments	2015-08-27 08:19:26 -06:00
sam_ethernet.c
sam_ethernet.h
sam_gpio.c
sam_gpio.h
sam_gpioirq.c
sam_hsmci_clkdiv.c
sam_hsmci.c
sam_hsmci.h
sam_irq.c	All ARMV7-M IRQ setup: Always set the NVIC vector table address. This is needed in cases where the code is running with a bootload and when the code is running from RAM. It is also needed by the logic of up_ramvec_initialize() which gets the vector base address from the NVIC. Suggested by Pavel Pisa	2015-08-21 08:42:24 -06:00
sam_lowputc.c
sam_lowputc.h
sam_mcan.c	SAMV7 MCAN: When bitrate is changed, the MCAN has to be reset and there are lots of issues related to getting back to a healthy state if there is multithreaded access to the MCAN device. This commit handles a few of those issues, but there are more	2015-08-18 11:56:07 -06:00
sam_mcan.h	SAMV7 MCAN: Remove SAMA5 kruft; beginning of some interrupt logic	2015-08-03 13:50:02 -06:00
sam_mpuinit.h
sam_periphclks.h
sam_qspi.c	Eliminate a warning	2015-09-01 13:35:38 -06:00
sam_qspi.h	SAMV71 QSPI: Use new QSPI interface. Can't use SPI interface as planned; the hardware architectue is too different	2015-08-25 15:23:59 -06:00
sam_serial.c
sam_spi_slave.c	SAMV7 SPI slave: Loop in the interrupt handler; RDRF and TXNE events should occur very closely in time	2015-08-11 09:30:24 -06:00
sam_spi.c	Rename sam_spi_slave_initialize to up_spi_slave_initialize for better symmety with the Master SPI interface definition	2015-08-09 17:41:55 -06:00
sam_spi.h	Rename sam_spi_slave_initialize to up_spi_slave_initialize for better symmety with the Master SPI interface definition	2015-08-09 17:41:55 -06:00
sam_ssc.c
sam_ssc.h
sam_start.c	Create a src directory for the STM32F7 (not much in it yet)	2015-07-15 14:32:28 -06:00
sam_start.h
sam_timerisr.c
sam_twihs.c
sam_twihs.h
sam_usbdev.h
sam_usbdevhs.c	SAMV7 USBHS DCD: Add logic to detect high speed mode; use DEBUGASSERT to check input parameters	2015-08-22 08:58:38 -06:00
sam_userspace.h
sam_xdmac.c
sam_xdmac.h	SAMV7 QSPI: Add DMA transfer support	2015-08-29 10:02:59 -06:00
samv71_periphclks.h