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addrenv.h
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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arm_addrenv_kstack.c
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Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err()
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2016-06-11 15:50:49 -06:00 |
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arm_addrenv_shm.c
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Replace all occurrences of vdbg with vinfo
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2016-06-11 11:59:51 -06:00 |
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arm_addrenv_ustack.c
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Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err()
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2016-06-11 15:50:49 -06:00 |
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arm_addrenv_utils.c
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Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err()
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2016-06-11 15:50:49 -06:00 |
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arm_addrenv.c
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Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err()
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2016-06-11 15:50:49 -06:00 |
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arm_allocpage.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_assert.c
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SMP: Fix typos in some conditional compilation
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2016-11-24 17:59:45 -06:00 |
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arm_blocktask.c
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Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs
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2016-03-09 13:41:48 -06:00 |
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arm_checkmapping.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_coherent_dcache.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_copyarmstate.c
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ARMv7-A/M: Cosmetic changes
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2015-12-14 11:56:39 -06:00 |
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arm_copyfullstate.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_cpuhead.S
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ARMv7-A/i.MX6: Add logic to handle allocation of CPU IDLE thread stacks more efficiently
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2016-05-13 11:39:42 -06:00 |
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arm_cpuidlestack.c
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ARMv7-A SMP: Allow CONFIG_SMP_NCPUS=1 for testing purposes
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2016-05-18 09:17:02 -06:00 |
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arm_cpuindex.c
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ARM: Remove some obsolete and incorrect conditional compilation
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2016-03-11 12:42:58 -06:00 |
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arm_cpupause.c
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arm_cpupause.c edited online with Bitbucke. What was I thinking... Back out previous change.
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2016-11-24 04:45:07 +00:00 |
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arm_cpustart.c
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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arm_dataabort.c
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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arm_doirq.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_elf.c
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armv7-a/armv6-m/arm/a1x: Convert *err() to either *info() or add ERROR:, depending on if an error is reported
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2016-06-17 16:44:50 -06:00 |
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arm_fpuconfig.S
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Make some file section headers more consistent with standard
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2015-04-08 08:04:12 -06:00 |
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arm_fullcontextrestore.S
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_gicv2_dump.c
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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arm_gicv2.c
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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arm_head.S
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Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES
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2016-06-11 14:14:08 -06:00 |
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arm_initialstate.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_l2cc_pl310.c
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armv7-a/armv6-m/arm/a1x: Convert *err() to either *info() or add ERROR:, depending on if an error is reported
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2016-06-17 16:44:50 -06:00 |
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arm_memcpy.S
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ARMv7-R: fix some issues to get a clean compilation; TMS570: Add enough logic to support a minimum build. Not much there on the initial commit
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2015-12-16 09:03:14 -06:00 |
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arm_mmu.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_pgalloc.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_pghead.S
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Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES
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2016-06-11 14:14:08 -06:00 |
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arm_pginitialize.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_physpgaddr.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_prefetchabort.c
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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arm_releasepending.c
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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arm_reprioritizertr.c
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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arm_restorefpu.S
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Cosmetic changes from review of last PR
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2016-04-18 06:50:45 -06:00 |
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arm_savefpu.S
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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arm_saveusercontext.S
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Cosmetic changes from review of last PR
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2016-04-18 06:50:45 -06:00 |
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arm_schedulesigaction.c
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ARMv7-A SMP: Add a little logic to signal handling.
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2016-11-24 11:45:05 -06:00 |
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arm_sigdeliver.c
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SMP: Add spin_trylock(). Use this in conditions where other CPUs need to stopped but we cannot call enter_critical_section.
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2016-11-24 13:33:43 -06:00 |
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arm_signal_dispatch.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_syscall.c
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Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info().
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2016-06-20 11:59:15 -06:00 |
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arm_testset.S
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Fix a cloned typo
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2016-10-19 09:14:21 -06:00 |
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arm_unblocktask.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_undefinedinsn.c
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Add underscore at beginning of alert() as well
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2016-06-16 12:38:05 -06:00 |
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arm_va2pte.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_vectoraddrexcptn.S
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Make some file section headers more consistent with standard
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2015-04-08 08:04:12 -06:00 |
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arm_vectors.S
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm_vectortab.S
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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arm_vfork.S
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More trailing whilespace removal
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2014-04-13 16:22:22 -06:00 |
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arm_virtpgaddr.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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arm.h
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ARMv7-A: Add GIC register definition header file
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2016-02-29 18:13:51 -06:00 |
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cache.h
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Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section()
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2016-02-13 19:11:09 -06:00 |
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cp15_cacheops.h
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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cp15_clean_dcache.S
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ARMv7-A: Update some co-processor register naming
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2015-12-14 13:04:03 -06:00 |
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cp15_coherent_dcache.S
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ARMv7-A: Update some co-processor register naming
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2015-12-14 13:04:03 -06:00 |
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cp15_flush_dcache.S
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ARMv7-A: Update some co-processor register naming
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2015-12-14 13:04:03 -06:00 |
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cp15_invalidate_dcache_all.S
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Make some file section headers more consistent with standard
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2015-04-08 08:04:12 -06:00 |
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cp15_invalidate_dcache.S
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ARMv7-A: Update some co-processor register naming
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2015-12-14 13:04:03 -06:00 |
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cp15.h
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ARMv7-A: Update some co-processor register naming
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2015-12-14 13:04:03 -06:00 |
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crt0.c
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SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
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2016-05-20 12:39:02 -06:00 |
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fpu.h
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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gic.h
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Centralize definitions associated with CONFIG_DEBUG_IRQ
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2016-06-15 08:35:22 -06:00 |
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gtm.h
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i.MX6: Add incomplete GPT header file
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2016-03-09 09:08:01 -06:00 |
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Kconfig
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Make it clear that GIC support is GICv2
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2016-03-14 10:50:54 -06:00 |
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l2cc_pl310.h
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arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache.
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2014-07-26 16:50:08 -06:00 |
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l2cc.h
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ARMv7-A: Cosmetic changes
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2015-12-14 08:42:39 -06:00 |
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mmu.h
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Remove a assertion condition that appears to rarely cause false-alarm assertions. Teported by Petteri Aimonen
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2016-11-21 14:43:56 -06:00 |
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mpcore.h
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MPCore: Fix missing header file inclusion; Add GIC-based implementations of up_enabable_irq(0 and up_disable_irq()
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2016-03-10 08:37:34 -06:00 |
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pgalloc.h
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This completes the implementation of shared memory support
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2014-09-24 09:27:17 -06:00 |
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sctlr.h
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Update some ARM registers for Cortex-A9
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2016-03-29 11:47:35 -06:00 |
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smp.h
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ARMv7-A/i.MX6: Add logic to handle allocation of CPU IDLE thread stacks more efficiently
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2016-05-13 11:39:42 -06:00 |
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svcall.h
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ARMv7-A/M: Cosmetic changes
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2015-12-14 11:56:39 -06:00 |
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Toolchain.defs
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WINTOOl should be selected only for Cygwin. MSYS and native should not have it.
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2016-01-09 16:34:33 -06:00 |
