Commit Graph

24 Commits

Author SHA1 Message Date
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-16 11:11:14 -03:00
ligd
3cfc6761ff xtensa: fix lack of float register save & resotre
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-01-11 12:17:09 +01:00
zhuyanlin
580d17cc02 arch:xtensa: make xtensa_abi.h global include and usage
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-06 07:39:27 -05:00
zhuyanlin
583dce0b98 arch:xtensa: remove WSBITS/WBBITS to core.h
Remove WSBITS/WBBITS macro to core.h as may be used by
arch common code.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-09-16 10:32:38 +08:00
zhuyanlin
e333733053 xtensa:coproc: fix XTENSA_CP_ALLSET error in some case
Consider follow coprocessor configuration case:

\#define XCHAL_CP_NUM                    1       /* number of coprocessors */
\#define XCHAL_CP_MAX                    2       /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK                   0x02    /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK              0x00    /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME                  "AudioEngineLX"
\#define XCHAL_CP1_IDENT                 AudioEngineLX
\#define XCHAL_CP1_SA_SIZE               208     /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN              8       /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX       1       /* coprocessor ID (0..7) */

In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.

Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
2021-08-10 19:44:55 -07:00
Alan C. Assis
7767acd24a Add initial ESP32S2 Xtensa support 2021-06-01 07:49:54 +02:00
Alin Jerpelea
cb2ecefbf1 arch: xtensa: fix nxstyle errors
Fix for errors reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-07 21:21:51 -05:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
chenwen
64e2f102ac xtensa/esp32: Add power management of force-sleep 2020-09-20 17:23:07 +01:00
Alan C. Assis
7a1342f503 Fix coding style and other small issues 2020-08-23 08:26:10 -06:00
Alan C. Assis
4ded03a673 ESP32: Add support to RNG HW Driver 2020-08-23 08:26:10 -06:00
YAMAMOTO Takashi
7774cdd7aa Appease many of nxstyle errors for esp32 related files
I skipped the following files because they were not simple.
I'll create separate PRs.

    arch/xtensa/src/esp32/esp32_cpustart.c
    arch/xtensa/src/common/xtensa_abi.h
    boards/xtensa/esp32/esp32-core/include/board.h

Also, I skipped the following files and directories because
they looked too huge and/or foreign.

    arch/xtensa/include/esp32/tie.h
    arch/xtensa/include/xtensa/xtensa_corebits.h
    arch/xtensa/src/esp32/hardware/
    arch/xtensa/include/esp32/tie-asm.h
    arch/xtensa/include/esp32/core-isa.h
    arch/xtensa/include/xtensa/core.h

I also fixed a few "is is" style typos when unwrapping long lines.
2020-03-12 07:45:44 -06:00
Xiang Xiao
bd4e8e19d3 Run codespell -w against all files
and fix the wrong correction
2020-02-22 14:45:07 -06:00
Gregory Nutt
1c5ec07414 arch/: Remove dangling space at the end of lines. 2017-06-28 13:16:48 -06:00
Gregory Nutt
588d2b506f Xtensa ESP32: Oddly, an rsync barrier when writing to co-processor register corrects problem. 2016-12-21 08:04:48 -06:00
Gregory Nutt
63d5ab5b67 Add logic to attach inter-CPU interrupts. Fix some compilation errors. 2016-10-30 16:15:04 -06:00
Gregory Nutt
d346f25aae Xtensa/ESP32: Fix some compile issues related to new co-processor logic 2016-10-29 10:27:46 -06:00
Gregory Nutt
ccf5b4e357 Xtensa: Cleanup of co-processor logic; remove some unnecessary things. 2016-10-29 09:36:33 -06:00
Gregory Nutt
be2a801e30 Xtensa: Add xtensa_coproc.h 2016-10-28 10:33:20 -06:00
Gregory Nutt
4cf60022ca Xtensa: Correct some compile issues 2016-10-23 16:25:55 -06:00
Gregory Nutt
6bbe55602c Xtensa: Add tie.h 2016-10-23 13:25:41 -06:00
Gregory Nutt
1fcced12eb Xtensa: Timer code now compiles okay 2016-10-23 11:31:48 -06:00
Gregory Nutt
9f06b13ffb Xtensa: Add core.h header file 2016-10-23 10:43:16 -06:00
Gregory Nutt
a9a4f6384d Xtensa: Add interrupt enable/disable controls. Add dummy timer and IRQ initialization. 2016-10-23 08:00:17 -06:00