Commit Graph

310 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
af8e71d9e9 risc-v/esp32c3: Fix inconsistent guard comment 2021-02-22 09:24:14 -08:00
Gustavo Henrique Nihei
628e2288aa risc-v/esp32c3: Add missing header guard for lowputc 2021-02-22 09:24:14 -08:00
Gustavo Henrique Nihei
ca30c1db69 risc-v/esp32c3: Build serial driver only when selected 2021-02-22 09:24:14 -08:00
Abdelatif Guettouche
491a4c1ed2 risc-v/esp32c3: Don't reserve any vectors for any special use.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-22 09:21:24 -08:00
Gustavo Henrique Nihei
291a5755cc risc-v/esp32c3: Add support for MWDT0 and MWDT1 2021-02-22 17:18:01 +00:00
Abdelatif Guettouche
067da56d0c esp32c3: Some cosmetics and style fixes.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-21 10:29:43 -03:00
Abdelatif Guettouche
10822799fb esp32c3: Add GPIO IRQ support.
The GPIO example was also extended to include testing an interrupt pin.

Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
2021-02-21 10:29:43 -03:00
Alan Carvalho
4a42998f36 esp32-c3: Add the GPIO driver.
This commits adds support for the ESP32-C3 IO Mux and GPIO Matrix.  It
also includes necessary board logic to run the GPIO example with 2
outputs.

Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-21 10:29:43 -03:00
Abdelatif Guettouche
4c3412faaa risc-v/esp32c3: Add clock configuration
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-18 01:21:53 -08:00
Sara Souza
998f7e5d4c risc-v/esp32c3: Add basic UART support for console 2021-02-18 01:21:53 -08:00
Dong Heng
b11a5ca8b2 risc-v/esp32c3: Add ESP32-C3 basic support
Co-authored-by: Dong Heng <dongheng@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-18 01:21:53 -08:00
David Jablonski
41bddc8461 litex: fix mtime and mtimecmp register address 2021-02-13 15:24:28 -08:00
David Jablonski
11167857c3 litex: nsh working 2021-02-13 15:24:28 -08:00
jpeng
af42079cc7 fix spi bug 2021-02-13 10:31:25 -08:00
liang
5914af84c7 arch/risc-v/bl602: spi_master support. 2021-02-13 10:31:25 -08:00
hotislandn
84daebf2cc arch:risc-v:bl602: enable FPU for this target. 2021-02-08 00:29:34 -08:00
Masayuki Ishikawa
d87f350831 arch, boards, drivers, include, sched, wireless: Change spinlock APIs.
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
  g_irq_spin for backword compatibility (In this case, NULL must be specified)

Impact:
- None

Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-07 21:28:56 -08:00
Abdelatif Guettouche
6547c3df55 arch/riscv: Fix file names in headers that were still using the old 'up_' prefix.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-05 21:19:20 -03:00
Abdelatif Guettouche
5447f28742 riscv: Remove the nx_start prototype from riscv_internal.h
This function is already declared in include/nuttx/init.h include this
file instead.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-02 17:48:40 -03:00
Abdelatif Guettouche
db2a8f0dc5 arch/risc-v: Remove incorrect ARM references.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-02 17:48:06 -03:00
Abdelatif Guettouche
37b93bd498 arch/risc-v: Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1.
Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1, so we won't
have to provide a dummy stub for every chip.
Also rename the function from up_addregion to riscv_addregion since it's
not exported outside the arch directory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-01 18:45:25 -08:00
Abdelatif Guettouche
52b4c73a61 arch/riscv: Remove references to MIPS.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-01-30 15:46:38 -08:00
Abdelatif Guettouche
0f2b774dec arch/risc-v: Remove unused and undefined file section "Public Variables"
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-01-27 18:40:10 -08:00
Xiang Xiao
94da3e4c3a arch: Remove critical section inside up_schedule_sigaction
since nxsig_tcbdispatch already hold it for us

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I2fe6ad840bdca3ec0eaa76a9af3b6929c7d5a721
2021-01-22 08:34:07 +01:00
liang
caf2d1430e arch/risc-v/bl602: add gpioirq and i2c(master) driver 2021-01-14 08:55:03 -08:00
liang
32708ab849 arch/risc-v/bl602 : add spiflash(hardware sf controller) 2021-01-11 17:59:00 -08:00
liang
2889315c20 arch/risc-v/bl602 : add pwm onshot watchdog driver. 2021-01-06 23:40:37 -08:00
Brennan Ashton
dd26d9c9f9 BL602: Add support for system reboot modes
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2021-01-02 00:14:37 -06:00
Brennan Ashton
c8db3293bb BL602: Use sig mask instead of number for AHB swrst 2020-12-30 23:27:42 -06:00
Brennan Ashton
e062bd08ce bl602: Update register defines and drivers 2020-12-30 23:27:42 -06:00
Virus.V
5f71e2be79 fix ci build failed 2020-12-29 01:52:09 -08:00
Virus.V
3e0a84182e check bl602 license 2020-12-29 01:52:09 -08:00
yangyue
d354a2f19f fix some code style 2020-12-29 01:52:09 -08:00
Virus.V
12258d72d2 Fix the BL602 mtimer frequency error. 2020-12-29 01:52:09 -08:00
Virus.V
2b8e0945a9 Fix BL602 CI Build failed.
Modify the default configuration in KConfig.
Sync latest commit from mainline.

Remove unused demo configuration

fixup bl602 nsh defconfig cause CICD failed

Rebase from mainline code
2020-12-29 01:52:09 -08:00
Virus.V
7e84874cb1 Reconstruct bl602 readme; move up_irq_save/restore declaration to common place 2020-12-29 01:52:09 -08:00
Virus.V
ce40edbd11 Solve the problems pointed out in the comments 2020-12-29 01:52:09 -08:00
Virus.V
417d0d4ccd fix checkpatch warning 2020-12-29 01:52:09 -08:00
Lei Chen
58bd873729 Add Basic support for BL602(UART timer CLIC) 2020-12-29 01:52:09 -08:00
liang
b074ebec9e fix redefined CSR_INSTRET 2020-12-23 01:34:14 -06:00
Masayuki Ishikawa
ec73a4e69c arch & sched: task: Fix up_exit() and nxtask_exit() for SMP
Summary:
- During repeating ostest with sabre-6quad:smp (QEMU),
  I noticed that pthread_rwlock_test sometimes stops
- Finally, I found that nxtask_exit() released a critical
  section too early before context switching which resulted in
  selecting inappropriate TCB
- This commit fixes this issue by moving nxsched_resume_scheduler()
  from nxtask_exit() to up_exit() and also removing
  spin_setbit() and spin_clrbit() from nxtask_exit()
  because the caller holds a critical section
- To be consistent with non-SMP cases, the above changes
  were done for all CPU architectures

Impact:
- This commit affects all CPU architectures regardless of SMP

Testing:
- Tested with ostest with the following configs
- sabre-6quad:smp (QEMU, dev board), sabre-6quad:nsh (QEMU)
- spresense:wifi_smp
- sim:smp, sim:ostest
- maix-bit:smp (QEMU)
- esp32-devkitc:smp (QEMU)
- lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-12-21 23:29:56 -06:00
Xiang Xiao
92cefb0a78 arch/risc-v: Move CSR register bit definition to csr.h
to avoid the macro duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-20 20:27:13 -08:00
Xiang Xiao
41d576f62b arch/riscv: Reuse the common up_schedule_sigaction implementation
to avoid the code duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-20 20:26:27 -08:00
Xiang Xiao
d42c5a0bf6 arch/risc-v: Move csr.h to common place
since CSR definition is same for 32bit and 64bit arch

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-19 08:41:33 +09:00
Xiang Xiao
fe8122ee2b arch/risc-v: Remove duplicated declaration for up_irq_save and up_irq_restore
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-19 08:29:42 +09:00
Abdelatif Guettouche
ecede04263 arch/*/src/Makefile: Generate dependencies for head files.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-12-15 21:00:52 -06:00
Xiang Xiao
625eef20f0 arch: Remove the special check for idle thread in up_use_stack
since the idle thread don't call up_use_stack anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-16 09:54:29 +09:00
Xiang Xiao
efee1c6ded arch: Initialize the idle thread stack info directly
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-16 09:54:29 +09:00
John Bampton
ba12c6c0cf Fix spelling 2020-12-12 19:18:08 +01:00
Masayuki Ishikawa
409c65ce0b arch, sched: Fix global IRQ control logics for SMP
Summary:
- This commit fixes global IRQ control logic
- In previous implementation, g_cpu_irqset for a remote CPU was
  set in sched_add_readytorun(), sched_remove_readytorun() and
  up_schedule_sigaction()
- In this implementation, they are removed.
- Instead, in the pause handler, call enter_critical_setion()
  which will call up_cpu_paused() then acquire g_cpu_irqlock
- So if a new task with irqcount > 1 restarts on the remote CPU,
  the CPU will only hold a critical section. Thus, the issue such as
  'POSSIBLE FOR TWO CPUs TO HOLD A CRITICAL SECTION' could be resolved.
- Fix nxsched_resume_scheduler() so that it does not call spin_clrbit()
  if a CPU does not hold a g_cpu_irqset
- Fix nxtask_exit() so that it acquires g_cpu_irqlock
- Update TODO

Impact:
- All SMP implementations

Testing:
- Tested with smp, ostest with the following configurations
- Tested with spresense:wifi_smp (NCPUS=2,4)
- Tested with sabre-6quad:smp (QEMU, dev board)
- Tested with maix-bit:smp (QEMU)
- Tested with esp32-core:smp (QEMU)
- Tested with lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-12-10 08:33:42 +01:00
Huang Qi
4078548ae3 risc-v: Introduce basic setjmp support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2020-12-04 09:40:07 -03:00
YAMAMOTO Takashi
e0d535c317 arch/risc-v/src/common/riscv_createstack.c: Fix a syslog format 2020-11-24 22:31:33 -08:00
YAMAMOTO Takashi
67ea358f96 arch/risc-v/src/litex/litex_schedulesigaction.c: Fix syslog formats 2020-11-24 22:31:33 -08:00
Masayuki Ishikawa
37dad5dd04 Revert "arch: k210: Fix the pause handler for SMP"
This reverts commit a500bd0238.
2020-11-25 00:02:37 +01:00
YAMAMOTO Takashi
21a84e4558 arch/risc-v/src/rv64gc/riscv_sigdeliver.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
9e04704cb6 arch/risc-v/src/k210/k210_schedulesigaction.c: Fix syslog formats 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
982061a9e0 arch/risc-v/src/rv64gc/riscv_swint.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
c934214bb3 arch/risc-v/src/rv32im/riscv_sigdeliver.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
d8c5095fa7 arch/risc-v/src/fe310/fe310_schedulesigaction.c: Fix syslog formats 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
263e4b991f arch/risc-v/src/rv32im/riscv_swint.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
YAMAMOTO Takashi
35449e4d14 risc-v: Don't use non existent "saved_status"
It seems like a copy-and-paste leftover from mips.
Replace them with saved_int_ctx.
(Shouldn't these files inherit the copyright notice from mips?)
2020-11-22 05:18:55 -08:00
YAMAMOTO Takashi
9ceb61d3a9 risc-v 64-bit: Fix SCN/PRI.PTR definitions 2020-11-22 05:18:29 -08:00
Matias N
d5b6ec450f Parallelize depend file generation 2020-11-22 09:02:59 -03:00
Masayuki Ishikawa
a500bd0238 arch: k210: Fix the pause handler for SMP
Summary:
- Apply the same logic added to cxd56_cpupause.c

Impact:
- SMP only

Testing:
- Tested with maix-bit:smp (QEMU)
- Run smp and ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-20 00:49:25 -08:00
YAMAMOTO Takashi
cce626b545 risc-v: Add _intmax_t and _uintmax_t 2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
e99321bf9d risc-v 32-bit: Fix types to match what the compiler expects
spacetanuki% riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -dM -E - < /dev/null | grep INT32_TYPE
    #define __INT32_TYPE__ long int
    #define __UINT32_TYPE__ long unsigned int
    spacetanuki% riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -dM -E - < /dev/null | grep INT64_TYPE
    #define __INT64_TYPE__ long long int
    #define __UINT64_TYPE__ long long unsigned int
    spacetanuki% riscv64-unknown-elf-gcc -dM -E - < /dev/null | grep LP64
    #define __LP64__ 1
    #define _LP64 1
    spacetanuki%
2020-11-19 00:49:56 -08:00
YAMAMOTO Takashi
723cc14009 risc-v: Switch int64_t from long long to long
So that it matches what the toolchain expects.

    spacetanuki% riscv64-unknown-elf-gcc --version
    riscv64-unknown-elf-gcc (SiFive GCC 8.3.0-2019.08.0) 8.3.0
    Copyright (C) 2018 Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.  There is NO
    warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

    spacetanuki% riscv64-unknown-elf-gcc -dM -E - < /dev/null | grep UINT64_TYPE
    #define __UINT64_TYPE__ long unsigned int
    spacetanuki%
2020-11-19 00:49:56 -08:00
zhongan
a396b191d4 rv32im: set compressed instruction enabled as default.
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-11-17 18:53:10 -08:00
zhongan
9eae6edfde rv32im: fix typo.
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-11-17 18:53:10 -08:00
YAMAMOTO Takashi
0390037472 arch/risc-v/src/gap8/gap8_uart.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
1170d0f71c arch/risc-v/src/fe310/fe310_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
ce7fae15e4 arch/risc-v/src/k210/k210_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
316ca6cd86 arch/risc-v/src/litex/litex_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
ee06d08548 arch/risc-v/src/nr5m100/nr5_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
f752b360f6 risc-v inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
Juha Niskanen
d65acc6db4 arch: serial: fix typos and run nxstyle
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2020-10-31 15:39:50 +01:00
Xiang Xiao
eb4121ce38 Change all 'Nuttx' to 'NuttX'
Unify the naming convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-10-20 01:45:06 -07:00
liuhaitao
d5c6bfe6cf arch: Add custom arch chip build support
Just like custom board build support, add custom arch chip build
support.

Change-Id: I71c87e6b2195501a1b1d728b71d7cbe344951057
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
2020-10-20 14:48:16 +08:00
Abdelatif Guettouche
609a5fa4f0 arch/: Add the ARCH_SRC directory to the context and clean_context
targets

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2020-10-17 22:46:27 +09:00
Yoshinori Sugino
444a05131c arch/risc-v/include: Fix nxstyle warnings
No functional changes
2020-10-10 14:24:52 +01:00
Yoshinori Sugino
aae4e15d9b arch/risc-v/src: Fix nxstyle warnings
No functional changes
2020-10-10 11:44:26 +01:00
Masayuki Ishikawa
e8ec8fb4b4 arch: risc-v: Fix up_interrupt_context() for SMP
Summary:
- Apply the same fix for Arm SMP

Impact:
- Affects SMP only

Testing:
- Tested with maix-bit:smp (qemu)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-09-30 08:32:25 -06:00
Yoshinori Sugino
3de85be15a arch/risc-v/src: Branch to up_sigdeliver() with interrupts disabled
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
2020-09-28 22:41:46 -07:00
Yoshinori Sugino
2adec1f366 arch/risc-v/src/fe310: Branch to up_sigdeliver() with interrupts disabled
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
2020-09-28 22:41:46 -07:00
Yoshinori Sugino
698008d1e5 Fix typos 2020-09-28 13:54:43 +08:00
zhongan
6240977341 rv32im: add missing call of 'up_savefpu'.
Change-Id: Iaf2e212a4fdea2f5f04a178d24755e0e37a30ef6
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-09-23 10:22:45 +01:00
zhongan
07dd053e86 risc-v: add putreg64 for mtimer registers.
Change-Id: I18fe312c95c73966f5c09fd18081b0c72923e2ac
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-09-23 10:22:45 +01:00
zhongan
657d1c9fdc Add and fix CSR macros listed in RISC-V spec V1.10.
Add csr operatiing macros.

Change-Id: Ia5c148d10709c21424c5ecaaca01b7d200fb8e01
Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-09-21 07:35:56 -07:00
Xiang Xiao
bf7399a982 arch: Initialize idle thread stack information
and remove the special handling in the stack dump

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia1ef9a427bd4c7f6cee9838d0445f29cfaca3998
2020-09-16 06:57:29 -07:00
Matias N
166242c171 use "export" to expose TOPDIR to all child make instead of passing it around every time 2020-09-15 21:11:33 -07:00
Matias N
3d1159007f Remove extra application of EXTRAFLAGS and KDEFINE and the arch-level
EXTRAFLAGS is already applied to *FLAGS in board's Make.defs (and
it applies to whole build, not just arch-code). EXTRAFLAGS is passed
around each make call to the complete build.

KDEFINE is already added to EXTRAFLAGS in main Makefile so no need
to add it again in arch-level Makefile
2020-09-14 13:59:57 +09:00
Xiang Xiao
b0797263ca libc/stdio: Allocate file_struct dynamically
1.Reduce the default size of task_group_s(~512B each task)
2.Scale better between simple and complex application

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia872137504fddcf64d89c48d6f0593d76d582710
2020-09-11 17:58:17 +08:00
Ouss4
06ca12e6b9 arch/: Trivial typos, mostly "their is" to "there is" 2020-09-09 14:09:43 -04:00
Xiang Xiao
f99719e260 Move note driver from drivers/syslog to drivers/note
it's better to put the note transport layer into a common folder

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-09-07 11:54:10 +08:00
Johannes Schock
515ad1c388 Added KDEFINE (__KERNEL__) to EXTRAFLAGS for libboard, for other architectures. 2020-09-05 21:25:31 +08:00
Masayuki Ishikawa
08c4376606 arch, include, sched : Refactor ARCH_GLOBAL_IRQDISABLE related code
Summary:
- ARCH_GLOBAL_IRQDISABLE was initially introduced for LC823450 SMP
- At that time, i.MX6 (quad Cortex-A9) did not use this config
- However, this option is now used for all CPUs which support SMP
- So it's good timing for refactoring the code

Impact:
- Should have no impact because the logic is the same for SMP

Testing:
- Tested with board: spresense:smp, spresense:wifi_smp
- Tested with qemu: esp32-core:smp, maix-bit:smp, sabre-6quad:smp
- Build only: lc823450-xgevk:rndis, sam4cmp-db:nsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-09-03 10:20:20 +08:00
Gregory Nutt
55a9172bc2 Fix Cygwin build with Windows native toolchain
PR #1450 broke the Cygwin build.  Refer to Issue #1672.

The use of of logic like:

    EXTRA_LIBPATHS += -L "${dir ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libgcc.a}}"

fails when the Toolchain $(CC) is a native Windows toolchain.  That is because the returned path is a Windows-style patch which cannot be handled by the make 'dir' command.  Commit 4910d43ab0 reorganized a lot of definitions and replaced the correct code with the use of the limit make 'dir' command.  The original code used the Bash dirname command which does not suffer from this limitation; it can handle both POSIX and Windows paths.

This was verified using the stm32f4discover:nsh toolchain with the Windows native ARM Embedded toolchain.  That toolchain returns:

    arm-none-eabi-gcc --print-file-name=libgcc.a
    c:/program files (x86)/gnu tools arm embedded/9 2019-q4-major/bin/../lib/gcc/arm-none-eabi/9.2.1/libgcc.a
2020-09-01 10:20:28 +08:00
Yoshinori Sugino
728d5efed6 arch/risc-v/src: Cosmetic change
Replace spaces with a tab
2020-08-14 10:27:23 +01:00
Xiang Xiao
28eed285c8 sched: The secondary idle threads should call nx_idle_trampoline
because nx_task_idle doesn't call sched_note_start. To avoid the
same error happen again in the furture, nx_task_idle is removed.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-07-29 16:03:13 +09:00
SPRESENSE
e249a2f82f Makefile: Fix Make.dep not updated by config changes
Make.dep file should be updated by .config changed after first make.
There are 2 cases affected for this problem:

 1) Add source files by config symbol
 2) Include header files in #ifdef directive

These 2 cases may not be included in Make.dep and this may prevent the
differential build from working correctly.
2020-07-28 03:59:45 -05:00