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375 Commits

Author SHA1 Message Date
Abdelatif Guettouche
2793e6f82d xtensa_releasepending.c: Remove commented out code. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-19 02:20:36 +08:00
Abdelatif Guettouche
d21d02c65d xtensa_panic.S: Save exception cause and vaddr into the user frame. 
This area is what's passed later to assert and be used to dump the
state.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 19:54:30 +08:00
Abdelatif Guettouche
a9e3b5ae37 xtensa_panic.S: A2 is already saved by the caller, no need to save it 
here again.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 19:54:30 +08:00
Abdelatif Guettouche
cff3d9df7b arch/xtensa: Fix some indentations. 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
6fa4a42e34 xtensa/: Save A3 as part of the regular context saving. 
It was separate because the syscal handler was using it before calling
_xtensa_context_save.  The order of operations has now changed and we
can save A3 with the rest of the context.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4d1bb20f8c xtensa_user_handler.S: In syscall handler store context before 
continuing the rest of the syscall handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5305f76b1d xtensa_context.S: Use Zephyr's version of spilling the window register 
file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2445de173d xtensa_dumpstate.c: Don't dump temporary registers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4786963ee2 xtensa_context.S: No need to save A2 before calling 
_xtensa_save_context.  It uses CALL0, in this case A1 is callee saved
and we can it directly.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2dcbf28f15 xtensa_context.S: A1 should be restored by the caller not 
xtensa_context_resotred. Here it was being restored twice.
Remove the one in xtensa_context_restore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5bd2e97a27 xtensa_context.S: Fix the type of _xtensa_context_restore. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
e9018b29bf xtensa_context.S: Remove the CALL0 ABI version of xtensa_context_switch 
as it's the same as the Window ABI now.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-14 11:12:35 +08:00
Xiang Xiao
c96c96a399 drivers: Merge the common driver initialization into one place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 11:24:48 -03:00
Xiang Xiao
39fb09738d arch: Move [arm|xtensa]_intstack_[alloc|top] to common header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-11 23:08:07 +02:00
Xiang Xiao
17d1a48fc9 arch: Remove up_puts prototype from up_inernal.h 
since it's defined in include/nuttx/arch.h now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-11 23:08:07 +02:00
Abdelatif Guettouche
f0a5777a26 xtensa_swint.c: Restore the coprocessor state at the end for consistency. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
7c57739d1d xtensa_exit.c: Co-processor state is restored as part of the 
SYS_Restore_context call, no need to call it separately.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
71ba4a6b76 arch/xtensa: Use the software interrupt when saving context too. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
329db99e51 arch/xtensa: Use rsync around manipulating interrupt registers and 
replace `isync` by `rsync` in other places.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-11 02:23:09 +02:00
zhuyanlin
634d337394 riscv/xtensa: corrent dumpstate xcp size 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-08 10:14:04 +02:00
zhuyanlin
981282696f xtensa:backtrace: fix backtrace last buffer error in some scene 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-07 10:21:37 +01:00
Abdelatif Guettouche
fa0e5da18e xtensa/xtensa_user_handler.S: Store EXCCAUSE and EXCVADDR into the user 
frame. The user frame is passed them to xtensa_user that actually uses
EXCVADDR.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-04 11:19:06 +02:00
zhuyanlin
a4e93be0fb arch:xtensa: fix sp duplicate reduce in handler enter 
In xtensa/include/irq.h the XCPTCONTEXT_SIZE is
`#define XCPTCONTEXT_SIZE    ((4 * XCPTCONTEXT_REGS) + 0x20)`

XCPTCONTEXT_SIZE is already byte size of xcpcontext

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-01 13:46:31 +01:00
Xiang Xiao
3bf416e8b8 arch: Move STACK_ALIGNMENT definition to up_internal.h 
to avoid the same macro duplicate to many place

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-28 15:05:41 +08:00
zhuyanlin
fbc1da98b7 xtensa: use swint to swith context 
Reason for use sw-interrupt as syscall interrupt:
The xtensa `syscall` instruction can cause SYSCALL interrupt.
But SYSCALL interrupt is same interrupt level with level-one
interrupt.
Nuttx swint can enter `enter_critical_section` and gerenate
interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-25 20:43:03 +08:00
zhuyanlin
7b00c8bdb8 arch:xtensa: modify svcall to swint 
Reason: xtensa svcall only have level-1 interrupt level.
Sush do not generate interrupt when up_irq_save.
Software int can generate interrupt when up_irq_save.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-22 14:06:24 -03:00
zhuyanlin
1b08f607be arm/xtensa:cache: flush/clean dcache all if size large than cache size 
For performance, if size large than cache size, use xxx_all instead

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-27 15:15:28 +08:00
Xiang Xiao
77792a1598 sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case 
to simplify the SMP related code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 23:21:21 +08:00
zhuyanlin
793ec6c909 arch:xtensa:vectors:fix bugs in a0 save 
Use right EXCSAVE_X

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
a1a9ce3d1e arch:xtensa_panic: use right interrupt pointer in xtensa_panic 
When enable interrupt stack, use a12 instead of sp

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
88f5a209ce xtensa: move a3 save in handler instead of _xtensa_context_save 
As in _xtensa_syscall_handler, a3 was save and reused before
_xtensa_context_save, a3 save in _xtensa_context_save will generate
error.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
561fa88ed1 xtensa: add svcall handler 
svcall.c for xtensa

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
662f071d9a xtensa: fix svccall enter error 
1. error in A3 push stack
2. when interrupt stack enable, push a12 is xtensa_irq_dispatch
parameter 1, instead of sp. As sp is interrupt stack address set by
`setintstack`, not the interruptee stack address

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-16 11:11:14 -03:00
chao.an
c27839f98e arm/xtensa: save the running registers to xcp context 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-15 02:20:01 +08:00
Gustavo Henrique Nihei
c372e1e295 xtensa: Fix typo in xchal_cpX_store macros' invocation 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-13 21:07:04 +01:00
ligd
3cfc6761ff xtensa: fix lack of float register save & resotre 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-01-11 12:17:09 +01:00
Zeng Zhaoxiu
fb43fd73ed signal: signal handler may cause task's state error 
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.

Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
 2022-01-05 21:36:44 +09:00
Abdelatif Guettouche
4edc5fb701 xtensa: Rename up_stack_color to xtensa_stack_color since it's an 
internal function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-01-04 02:45:45 +08:00
Petro Karashchenko
d23ad9b9b0 userspace: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-02 20:50:30 +01:00
chao.an
736add0fe8 arch/backtrace: correct the skip counter 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-30 16:57:40 +08:00
Xiang Xiao
dd942f0b04 sched/backtrace: Dump the complete stack regardless the depth 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-29 12:09:54 +08:00
chao.an
fe2830ec94 xtensa: enhance the task dump 
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-22 11:46:02 -03:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:02:12 -03:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump 
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-15 12:00:35 -06:00
chao.an
56ef1419dd arch/xtensa: set the current reg before print syslog 
ensure the semantics of the up_interrupt_context() works as expected

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-14 21:40:03 -06:00
chao.an
2fe06ac083 arch: xtensa: save current SP before overwrting 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-14 21:40:03 -06:00
chao.an
93b133fe66 arch/xtensa: correct the interrupt stack on irq handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-14 21:40:03 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit 
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-06 11:23:58 +09:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0] 
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-01 16:04:15 +01:00