Xiang Xiao
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2956b8516b
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Fix nxstyle warning
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2020-10-20 01:45:06 -07:00 |
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Xiang Xiao
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eb4121ce38
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Change all 'Nuttx' to 'NuttX'
Unify the naming convention
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2020-10-20 01:45:06 -07:00 |
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Dave Marples
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d0cda60442
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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ahb
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67c86e5aa9
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add LPC4337FET256
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2017-03-09 10:30:28 +01:00 |
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Gregory Nutt
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f06a06952f
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LPC43xx: 1KB is 1024, not 1025. Noted by phreakuencies.
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2016-05-31 06:22:10 -06:00 |
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Alexander Vasiljev
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ad6f37edfa
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Adds definitions for the LPC4337jet100 chip.
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2016-05-24 07:03:50 -06:00 |
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Gregory Nutt
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83bc1c97c3
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Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()
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2016-02-14 16:11:25 -06:00 |
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Lok Tep
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1f4ce9e7f9
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LPC43xx: Fix some NVIC priority definitions
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2016-01-25 07:23:28 -06:00 |
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Lok Tep
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3b4c71ef8d
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more revert
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2015-11-09 14:51:00 +01:00 |
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Lok Tep
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a8416d2a26
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revert
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2015-11-09 14:41:08 +01:00 |
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Lok Tep
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7d386866af
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Merged nuttx/arch into master
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2015-11-09 14:24:41 +01:00 |
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v01d
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79fad2843a
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lpc4337: WIP
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2015-10-30 20:15:18 -03:00 |
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Lok Tep
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5983019a45
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merge from nuttx
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2015-10-08 22:57:34 +02:00 |
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Gregory Nutt
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3a07b09b9a
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LPC43xx: Tweaks to pkolesnikov's LPC4370 changes to get a clean compilation
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2015-10-01 10:00:25 -06:00 |
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petekol
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0eb1afcdef
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usb reset right
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2015-09-30 17:13:32 +02:00 |
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petekol
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585fdf70d8
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CONFIG_ARCH_CHIP_LPC4370FET100
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2015-09-29 17:23:17 +02:00 |
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Ilya Averyanov
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675878b360
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PC43xx: Fix NVIC_SYSH_PRIORITY_STEP define
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2015-09-01 08:06:34 -06:00 |
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Gregory Nutt
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3855ce04e8
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Beginning of high priority nested interrupt support for the ARMv7-M family
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2013-12-21 11:03:38 -06:00 |
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patacongo
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5ab31d456e
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Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
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2013-01-22 01:25:40 +00:00 |
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patacongo
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231e9e262d
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Add support to the LPC4330-Xplorer port for the Code Red toolchain
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4920 42af7a65-404d-4744-a932-0658087f49c3
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2012-07-08 22:28:39 +00:00 |
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patacongo
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53bb15a078
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Add LPC43 clock initialization logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4910 42af7a65-404d-4744-a932-0658087f49c3
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2012-07-05 22:38:12 +00:00 |
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patacongo
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899eb0b5ce
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Add LPC43 Event Monitor, EEPROM, FLASH header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4898 42af7a65-404d-4744-a932-0658087f49c3
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2012-07-02 22:15:20 +00:00 |
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patacongo
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089c4a508c
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Beginning of NXP LPC4330 port
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4876 42af7a65-404d-4744-a932-0658087f49c3
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2012-06-27 19:17:30 +00:00 |
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