The main features are:
1. DMA2D interface
Supports the nuttx pixel formats:
- FB_FMT_RGB8
- FB_FMT_RGB24
- FB_FMT_RGB16_565
Dynamic layer allocation during runtime for the supported formats
- The number of allocatable layer can be configured.
Supported dma2d operation:
- blit (Copy content from source to destination layer) also works with
selectable area.
- blend (Blend two layer and copy the result to a destination layer wich can
be a third layer or one of the source layer) also works with selectable
area.
- fillarea (Fill a defined area of the whole layer with a specific color)
As a result of that the dma2d controller can't transfer data from the core coupled memory, CCM is disabled but usable by the ccm allocator. Currently the ccm allocator is used for allocating the layer structurei only. For the dma memory (layers frame buffer) memory is allocated from heap 2 and 3.
2. LTDC interface
I have changed the api for the currently non implemented operations:
- blit (Copy content from a dma2d layer to an ltdc layer) also works with
selectable area.
- blend (Blend two dma2d layer and copy the result to a destination ltdc
layer) also works with selectable area.
Note! ltdc layer is a layer referenced by the ltdc interface. dma2d layer
is a layer referenced by the dma2d interface.
One of the most important questions for me was, How can i flexible use an
ltdc layer with the dma2d interface, e.g. as source layer for dma2d
operations?
Get the layer id of the related dma2d layer by a special flag when using
getlid() function of the ltdc interface and use the layer id to reference
the specific dma2d layer by the dma2d interface.
The ltdc coupled dma2d layers are predefined and can't be dynamically
allocated of freed. They use the same frame buffer memory and the same
color lookup table.
Changes:
- layer internal format of the clut table
- interrupt handling for register reload (vertical vblank) instead using
waiting loop
- small fixes and refactoring
From Marco Krahl.
A side-effect of changing serial settings via TERMIOS (such as tcsetattr) is that serial interrupts were being left disabled. This is not a problem if the serial configuration is changed when there are no open references to the serial device. In that case, serial interrupts are disabled and will not be enabled enabled until the serial device is first opened. But it is fatal if the serial device is already opened and if there is a task waiting to receive data. In that case, the side-effect of disabling interrupts is fatal: That task is then left hanging with interrupts disabled.
In stm32_rtcc.c the up_rtcinitialize() logic doesn't work with the LSI. The check on RTC_MAGIC on the BK0R register lead to rtc_setup() call that rightfully enables the lsi clock; but the next times, when the rtc is already setup, the rtc_resume() call does NOT start the lsi clock!
The right place to put LSE/LSI initialisation is inside stm32_stdclockconfig() in stm32fxxxxx_rcc.c. Doing this I checked the possible uses of the LSI and the LSE sources: the LSI can be used for RTC and/or the IWDG, while the LSE only for the RTC (and to output the MCO1 pin)..
This change is not verifed for any other platforms.
From Leo Aloe3132
SAMV7 Ethernet: I- and D-Cache are now enabled in the netnsh/ configuration. D-Cache is enabled in write-though mode. This mode is necessary because the DMA descriptors are each 8-bytes in size but the D-Cache cache line is 32-bits in size. So it is impossible make coherency for every 8-byte DMA descriptor without write-through.
