when executing ioctl AUDIOIOC_GETBUFFERINFO,the priv->pcm is still NULL,
so it will return -ENXIO,we can remove this check at the start of ioctl
and add in the case where it is used.
Signed-off-by: shipei <shipei@xiaomi.com>
When supporting high-priority interrupts, updating the
g_running_tasks within a high-priority interrupt may be
cause problems. The g_running_tasks should only be updated
when it is determined that a task context switch has occurred.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
stack_t used by sigaltstack, make it compile sucess in sim.
Signed-off-by: yangyalei <yangyalei@xiaomi.com>
ltp: fix compile errors
Signed-off-by: yangyalei <yangyalei@xiaomi.com>
Instead of clearing the fields individually, just wipe the whole register.
This can be done because flags and rm are just parts of the fcsr.
31 8 5 0
+--------------+--------+-----------+
| | | |
| RESERVED | FRM | FSTATUS |
| | | |
+--------------+--------+-----------+
FCSR
- Save the FPU registers into the tcb so they don't get lost if the stack
frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
- Save ONLY if FPU is dirty
- Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.
Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
In the init phase of the OS, arch_get_current_tcb return NULL. Enable
the memory backatrace default will crash in backtrace function.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
If the cache is already enabled before NuttX starts up,
enabling the cache in NuttX will cause the cache to be
re-invalidated, then resulting in data that is already
in the cache being flushed out.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Basically, it reserves an area of the RTC memory to preserve the
RTC timer.
Please refer to:
fa76c82a5b
This commit also removes the rtc.dummy section because C3, C6 and
H2 don't need to skip it once the region is accessed by the same
address space using the instruction and data bus.
1. add lib_fork api in libs/libc, we need a fork() api to implement the
fork relative method, such as pthread_atfork
2. rename the assembly fork entry function name to up_fork(), and rename
the up_fork() to arch specific name, such as
sim_fork()/arm_fork()/mips_fork() etc.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Clone the esp-hal-3rdparty repository and, then, checkout to a
specific version (usually indicated by the commit SHA) instead of
using a branch as the HEAD.
Also switch to automatic one by default, as it saves a lot of flash. The manual training
code is left in for now to be able to use it as an option if there are problems with automatic one
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The implementation of up_perf_*() is in a different static library in nuttx:
Hardware: libarch.a
Software: libdrivers.a (weak function)
Since functions with weak attributes cannot be correctly replaced in multiple static libraries,
this PR will use macros to replace whether the arch supports hardware perf events
Signed-off-by: chao an <anchao@xiaomi.com>
If -fstack-protector-all is enabled, gcc linker will need GCC
SSP(Stack Smashing Protector) support, Since the implement of SSP
is related to the OS, most of embedded toolchain does not provide
ssp support, so an error will be reported when linking:
enable CONFIG_LTO_FULL && CONFIG_STACK_CANARIES
arm-none-eabi/bin/ld: cannot find -lssp_nonshared: No such file or directory
arm-none-eabi/bin/ld: cannot find -lssp: No such file or directory
https://github.com/gcc-mirror/gcc/blob/master/gcc/gcc.cc#L983-L985
Since nuttx has already implemented SSP related hook functions,
so in this PR, we filter out this option in the link phase to ensure that
the implementation of lssp/lssp_nonshared will not be referenced
Signed-off-by: chao an <anchao@xiaomi.com>
Writes to MPFS_CFG_DDR_SGMII_PHY_EXPERT_DFI_STATUS_OVERRIDE register were not done properly. Use correct address for writes.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Reading the CSD field misses 3 bytes as the residual bytes
are not carried over properly. Fix this by adding the missing
bytes due to shifting.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
According to the ARMv7a/r/m and ARMv8m architecture manuals
The allowed values are
0 Data or unified cache.
1 Instruction cache.
"One CCSIDR is implemented for each cache that can be accessed by the processor. CSSELR selects which Cache Size ID Register is accessible, see c0, Cache Size Selection Register (CSSELR)."
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Remove TABs
Fix indentation
Fix Multi-line comments
Fix Comments to the Right of Statements.
Fix nuttx coding style
Fix Comments to the Right of Statements.
In the current implementation of other architectures, it is not really implemented to preserve the context, so it is emulated from other architectures to clear the context.
If this behavior is not implemented, it will cause the xtensa architecture processor to loop assert in the active assert case
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
1. as we can use fork to implement vfork, so we rename the vfork to
fork, and use the fork method as the base to implement vfork method
2. create the vfork function as a libc function based on fork
function
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
