Xiang Xiao
7990f90915
Indent the define statement by two spaces
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follow the code style convention
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-21 09:52:08 -03:00
Xiang Xiao
6f6fce95a2
Replace all sprintf with snprintf
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-08 09:57:01 +02:00
Nathan Hartman
5f9cb6faf4
drivers/serial: Fix docstrings on UART interrupt handlers
2023-02-07 04:41:36 +08:00
Xiang Xiao
d5689e070b
net/arp: Remove nuttx/net/arp.h
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1.move ARPHRD_ETHER to netinet/arp.h
1.move arp_entry_s to net/arp/arp.h
2.move arp_input to nuttx/net/netdev.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-16 22:10:59 +02:00
Xiang Xiao
c6e9edcbb6
net: Rename arp_arpin to arp_input
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align with other similar function(e.g. ipv4_input and ipv6_input)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-04 20:39:21 +08:00
chao an
6fa60627eb
net/devif/ip: build l2 header on the IP layer
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Signed-off-by: chao an <anchao@xiaomi.com>
2022-11-27 12:13:45 +08:00
chao an
8850dee746
net/devif: move preprocess of txpoll into common code
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Signed-off-by: chao an <anchao@xiaomi.com>
2022-11-27 12:11:12 +08:00
Xiang Xiao
6b31918b42
Remove the unnecessary cast for main_t, NULL and argv
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-18 08:51:45 +02:00
Xiang Xiao
3c1c29f2c4
arch: move non arm g_current_regs defintion to common place
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to avoid the code duplicaiton
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-21 22:23:11 +02:00
Petro Karashchenko
b3cd9090d1
drivers/net: make sure that net driver d_buf is 16-bit aligned
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-08-05 22:21:37 +08:00
zhanghongyu
035d925864
devif: remove all devif_timer
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Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2022-06-02 20:11:50 -03:00
Xiang Xiao
03c31d332f
arch/arm: Remove FAR and CODE from chip folder(1)
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-03 16:50:52 +03:00
chao.an
3ec2f70046
arch/arm/Make.defs: unify arch common source include
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-30 21:50:16 +08:00
chao.an
a560eb5f8d
arch/arm/Make.defs: unify common source include
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-30 21:50:16 +08:00
Xiang Xiao
ebf1093cff
arch/arm: Switch the context of save and restore from assembler to c
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-21 12:56:34 +03:00
chao.an
81130bc692
arch/arm: remove unused arm_copyfullstate/arm_copyarmstate
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-15 23:03:51 +09:00
chao.an
7b9978883c
arch/arm: optimize context switch speed
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The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-15 23:03:51 +09:00
chao.an
7c02432f0e
arm/armv7-a/r: set the default CPU mode to System
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In SVC mode, the banked register will be inconsistent with the user mode register:
arch/arm/src/armv7-a/arm_vectors.S
276 .globl arm_syscall
277 .globl arm_vectorsvc
278 .type arm_vectorsvc, %function
279
280 arm_vectorsvc:
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286 sub sp, sp, #XCPTCONTEXT_SIZE // < SVC mode SP
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308 stmia r0, {r13, r14}^ // < USR mode SP/LR
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[ 2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[ 2.200000] [ 4] [ ALERT] R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[ 2.200000] [ 4] [ ALERT] R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[ 2.200000] [ 4] [ ALERT] CPSR: 00000073
[ 2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[ 2.200000] [ 4] [ ALERT] R0: 1 80202018 1 80202018 0 0 0 802027d0
[ 2.200000] [ 4] [ ALERT] R8: 0 0 0 0 0 802027d0 1080f710 80001229
[ 2.200000] [ 4] [ ALERT] CPSR: 00000070
SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE
[ 2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[ 2.200000] [ 4] [ ALERT] R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[ 2.200000] [ 4] [ ALERT] R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[ 2.200000] [ 4] [ ALERT] CPSR: 00000070
[ 2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[ 2.200000] [ 4] [ ALERT] R0: 2b 0 80202780 0 0 0 0 80202710
[ 2.200000] [ 4] [ ALERT] R8: 0 0 0 0 0 10843d80 800039d5 10801425
[ 2.200000] [ 4] [ ALERT] CPSR: 00000073
SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode
This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-14 19:54:53 +09:00
Xiang Xiao
54e630e14d
arch: Merge up_arch.h into up_internal.h
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 09:32:17 +02:00
Petro Karashchenko
fc9e2d272e
arch/arm/arm[-a|-r]: fix typos in comments
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-11 11:08:01 +08:00
Xiang Xiao
a07dc2363e
c5471/c5471_irq.c: Fix error: '__builtin_memcpy' forming offset [4, 31] is out of the bounds [0, 4] of object '_svectors' with type 'int'
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-10 19:46:01 +02:00
chao.an
6cc0aaf5b9
arch/arm: unify switch context from software interrupt
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 15:04:29 +09:00
Huang Qi
95b0c85f58
arch: Add xxx_tcbinfo.c to SoC level Make.defs
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Fix build break with CONFIG_DEBUG_TCBINFO enabled.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-12 21:07:35 +09:00
Xiang Xiao
4c167b0729
Correct the code alignment
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-01 21:22:21 -03:00
Xiang Xiao
2935751bfd
Fix error: implicit declaration of function 'up_cpu_index'
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Petro Karashchenko
08043fb5bc
net: unify FAR keyword usage for all net buffer memory mapped buffers
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-20 01:42:56 +08:00
Petro Karashchenko
9551de7115
net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-18 10:59:47 +01:00
Xiang Xiao
75a119ac1c
arch: Compile up_puts in all Make.defs
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-09-18 07:33:44 -03:00
ligd
aac0db368c
ARM: fix CPSR corruption after exception handling
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It seems to be caused by the corrupted or wrong CPSR restored on return
from exception. NuttX restores the context using code like this:
msr spsr, r1
GCC translates this to:
msr spsr_fc, r1
As a result, not all SPSR fields are updated on exception return. This
should be:
msr spsr_fsxc, r1
This bug has been fixed by Heesub Shin in:
343243c7c0
Change-Id: Ibc64db7bceecd0fb6ef39284fb5bc467f5603e2e
2021-07-19 08:41:06 -03:00
Xiang Xiao
2e54df0f35
Don't include assert.h from public header file
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-03 08:36:03 -07:00
Xiang Xiao
8640d82ce0
arch: Rename g_intstackbase to g_intstacktop
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-16 12:41:41 +09:00
Xiang Xiao
3f67c67aaf
arch: Fix the stack boundary calculation and check
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All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-10 08:39:54 -07:00
Xiang Xiao
eeb8931c04
arch/arm: align arm vector related code with armv7-a
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commit 3c30c8b90b
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Tue Apr 6 15:47:27 2021 +0800
arch/arm: Remove g_irqtmp, g_undeftmp and g_aborttmp
to avoid multiple CPU access them concurrently in SMP case
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-07 16:18:27 +09:00
Xiang Xiao
0779f34390
arch/arm: Add PSR_ prefix to the mode state like armv7-a
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no real function change
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-07 16:18:27 +09:00
Xiang Xiao
a7f7796db1
arch/arm: Change all spsr_cxsf to spsr
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unify the SPSR register usage
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-07 06:44:37 +09:00
Xiang Xiao
2268c19171
arch/arm: Fix the style issue in assemble files
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remove the unused header file and mimic the difference between sub arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-04-04 14:39:16 +01:00
Alin Jerpelea
d1e4a0cc28
arch: arm: c5471: fix nxstyle errors
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Fi nxstyle errors to pass CI
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-25 01:34:38 -07:00
Alin Jerpelea
197729e1ff
arch: arm: c5471: Author Gregory Nutt: update licenses to Apache
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Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-25 01:34:38 -07:00
Alin Jerpelea
bd94263a33
arch: Makefile: Author Gregory Nutt: update licenses to Apache
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Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-13 05:56:43 -08:00
Gustavo Henrique Nihei
330eff36d7
sourcefiles: Fix relative path in file header
2021-03-09 23:18:28 +08:00
Gustavo Henrique Nihei
47cb41c92f
makefiles: Fix relative path in file header
2021-03-09 23:18:28 +08:00
chao.an
4a559807a5
arch/netdev: try tcp timer in every txavail call
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In the current implementation, the first transmission of the new
connection handshake is depends entirely by tcp_timer(), which will
caused 0.5s - 1s delay each time in connect().
This patch is mainly to improve the performance of TCP handshake.
Original:
nsh> tcp_client
[ 1.536100] TCP connect start.
[ 2.000200] TCP connect end. DIFF: tick: 4641, 464ms.
[ 3.000300] TCP connect start.
[ 4.000400] TCP connect end. DIFF: tick: 10001, 1000ms.
[ 5.000500] TCP connect start.
[ 6.000600] TCP connect end. DIFF: tick: 10001, 1000ms.
[ 7.000700] TCP connect start.
[ 8.000800] TCP connect end. DIFF: tick: 10001, 1000ms.
Optimized:
nsh> tcp_client
[ 3.263600] TCP connect start.
[ 3.263700] TCP connect end. DIFF: tick: 1, 0ms.
[ 4.263800] TCP connect start.
[ 4.263800] TCP connect end. DIFF: tick: 0, 0ms.
[ 5.263900] TCP connect start.
[ 5.263900] TCP connect end. DIFF: tick: 0, 0ms.
[ 6.264000] TCP connect start.
[ 6.264000] TCP connect end. DIFF: tick: 0, 0ms.
[ 7.264100] TCP connect start.
[ 7.264100] TCP connect end. DIFF: tick: 0, 0ms.
Signed-off-by: chao.an <anchao@xiaomi.com>
2020-12-18 14:16:11 +09:00
YAMAMOTO Takashi
b176086ace
arch/arm/src/c5471/c5471_ethernet.c: Fix syslog formats
2020-11-28 23:14:05 -06:00
YAMAMOTO Takashi
0abb5d9c9d
arch/arm/src/c5471/c5471_watchdog.c: Fix syslog formats
2020-11-28 23:14:05 -06:00
YAMAMOTO Takashi
10a4243fcf
arch/arm/src/c5471/c5471_watchdog.c: Fix printf format warnings
2020-11-16 08:29:00 -08:00
YAMAMOTO Takashi
6ec164d553
arch/arm/src/c5471/c5471_watchdog.c: Appease nxstyle
2020-11-16 05:46:53 -08:00
Masayuki Ishikawa
973a6c49b6
arm, c5471: Refactor interrupt stack related code
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Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects arm (arm7/9) and c5471 with interrupt stack enabled
Testing:
- Built with c5471evm.nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Built with ea3131:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-10-26 09:05:49 -07:00
Xiang Xiao
acca9fcc3b
sched/wdog: Remove MAX_WDOGPARMS and related stuff
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since the variable arguments are error prone and seldom used.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-08-14 08:19:50 -06:00
Xiang Xiao
a0ce81d659
sched/wdog: Don't dynamically allocate wdog_s
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to save the preserved space(1KB) and also avoid the heap overhead
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I694073f68e1bd63960cedeea1ddec441437be025
2020-08-11 12:28:55 -06:00
Xiang Xiao
f618de9c97
Fix nxstyle warning
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-08-08 17:30:26 -03:00