According the Datasheet the WDD Value is the lower bound of a so called Forbidden Window and to disable this we have to set the WDD
Value greater than or equal to the WDV Value. This seems to be a bug in the datasheet. It looks like we have to set it to a greater value than the WDV to realy disable this Thing. When triggering the Watchdog faster than the (very slow) clock source of the Watchdog fires, this Forbidden Window Feature resets the System if WDD equals to WDV.
This Changeset disables the Forbidden Window by setting the WDD Value to the Maximum (0xfff) Value possible.
Combination of RXDMA + IFLOWCONTROL does not work as one might expect.
Since RXDMA uses circular DMA-buffer, DMA will always keep reading new
data from USART peripheral even if DMA buffer underruns. Thus this
combination only does following: RTS is asserted on USART setup and
deasserted on shutdown and does not perform actual RTS flow-control.
Data loss can be demonstrated by doing long up_mdelay inside irq
critical section and feeding data to RXDMA+IFLOWCONTROL UART.
Zero wait-state for flash can be configured when:
Range 1 and SYSCLK <= 16 Mhz
Range 2 and SYSCLK <= 8 Mhz
Range 3 and SYSCLK <= 4.2 Mhz
Medium performance voltage range (1.5V) can be configured when SYSCLK is up to 16 Mhz and PLLVCO up to 48 Mhz.
1) Revert the inherited dma bug from the stm32
see df9ae3c13f
for details.
2) Most all CR1-CR3 settings can not be configured while UE
is true. Threfore we make all operation atomic and disable
UE and restore it's originalstate on exit.
Writing to a flash sector while starting the erase of other sector
have a undefined behavior so lets add a semaphore and syncronize
access to Flash registers.
But for the semaphore to work it needs to be initialized so each
board needs call stm32_flash_initialize() on initialization, so
to avoid runtime problems it is only using semaphore and making
it thread safe if initialized, after all boards starts to call
stm32_flash_initialize() we can remove the boolean and the check.
