Jussi Kivilinna
4c99a6aeec
STM32F7: serial: do not stop processing input in SW flow-control mode
2017-04-11 06:40:44 -06:00
Jussi Kivilinna
e9a8dc7c6e
STM32F7: serial: disallow broken configuration combination of CONFIG_STM32F7_FLOWCONTROL_BROKEN=y and CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS not set.
2017-04-11 06:39:27 -06:00
Jussi Kivilinna
0aa52d98a2
STM32F7: add warning for RXDMA + IFLOWCONTROL combination
...
Combination of RXDMA + IFLOWCONTROL does not work as one might expect.
Since RXDMA uses circular DMA-buffer, DMA will always keep reading new
data from USART peripheral even if DMA buffer underruns. Thus this
combination only does following: RTS is asserted on USART setup and
deasserted on shutdown and does not perform actual RTS flow-control.
Data loss can be demonstrated by doing long up_mdelay inside irq
critical section and feeding data to RXDMA+IFLOWCONTROL UART.
2017-04-06 08:47:45 -06:00
Jussi Kivilinna
e2702cbe4e
STM32F7: fix UART7 and UART8 IFLOWCONTROL options
2017-04-06 08:46:24 -06:00
Jussi Kivilinna
dabf45f100
STM32F7: default CONFIG_STM32F7_DMACAPABLE to 'n'. STM32F7 does not have CCM RAM but DTCM, so this option does not need to enabled. DTCM RAM is DMA-able through CPU AHBS bus.
2017-04-06 08:44:53 -06:00
Jussi Kivilinna
e180522854
stm32f7: serial: add interface to get uart_dev_t by USART number, stm32_serial_get_uart
2017-04-06 08:41:41 -06:00
David Sidrane
fbb6cfc79c
stm32f7:Serial fix for dropped data
...
1) Revert the inherited dma bug from the stm32
see df9ae3c13f
2017-03-31 13:17:34 -10:00
Gregory Nutt
70182bf690
Fix more problems found in build testing.
2017-02-28 11:34:03 -06:00
Gregory Nutt
61639c1aa3
STM32 F7 Serial: Convert to use new interrupt argument interface.
2017-02-28 10:58:22 -06:00
Mark Schulte
b3222bbc8a
irq_dispatch: Add argument pointer to irq_dispatch
...
Provide a user defined callback context for irq's, such that when
registering a callback users can provide a pointer that will get
passed back when the isr is called.
2017-02-27 06:27:56 -06:00
David Sidrane
06036a5841
stm32_serial.c edited online with Bitbucket
2016-07-08 01:56:37 +00:00
Gregory Nutt
72de45b7cf
Merged in david_s5/nuttx/upstream_to_greg (pull request #21 )
...
Fixed Break changes needed CONFIG_SERIAL_TERMIOS to build
2016-05-17 18:09:23 -06:00
David Sidrane
f444f061d6
Fixed Break changes needed CONFIG_SERIAL_TERMIOS to build
2016-05-17 14:04:51 -10:00
Gregory Nutt
5fc619eb1b
Changes from review of last PR
2016-05-17 17:39:27 -06:00
David Sidrane
3ffe7c378f
Support BSD compatible breaks on stm32f7 U[S]ART
2016-05-17 13:09:34 -10:00
David Sidrane
55d8b0e277
Use the correct register and bit to send an STM32 non-bsd compatible break
2016-05-17 07:55:33 -10:00
Gregory Nutt
050f544782
Fix typo in variable name in serial BREAK logic. Review other serial implementations for similar naming problems.
2016-05-05 11:30:47 -06:00
Gregory Nutt
267e20c729
PM: Add domain to all PM interfaces. Internal PM data structures now handle multiple PM domains.
2016-03-27 13:01:32 -06:00
Gregory Nutt
32acc35c88
PM: Add activity domain to all PM callbacks
2016-03-27 11:18:54 -06:00
Gregory Nutt
9c63736c98
Standard some naming if code sectino comments
2016-02-21 18:06:09 -06:00
Gregory Nutt
70e502adb0
Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section()
2016-02-13 19:11:09 -06:00
Gregory Nutt
7dbfae87ec
STM32 F7: Correct some spacing issues
2015-10-07 13:58:11 -06:00
Paul A. Patience
a0dc724a5d
Correct #if to #ifdef when the macro can be undefined. Fix bug in AT32UC3 clock initialization: AVR32_CLOCK_PLL_OSC1 should be AVR32_CLOCK_PLL0_OSC1 and AVR32_CLOCK_PLL1_OSC1.
2015-09-01 13:47:06 -04:00
Gregory Nutt
2ce3c75264
STM32 F7 Ethernet: Add logic to align all DMA memory to the D-Cache line size
2015-07-19 16:35:25 -06:00
Gregory Nutt
3150706ee4
STM32 F7: Add logic to enable I-/D-Cache, ITCM and DTCM
2015-07-19 10:43:26 -06:00
Gregory Nutt
be008484e7
STM32 F7: Port the STM32 F3 serial driver to the STM32 F7
2015-07-19 09:25:27 -06:00
