sergiotarxz/nuttx
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114 Commits

Author SHA1 Message Date
Xiang Xiao
df5a8a53ae arch/arm: Move FPU initialization to common place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 23:35:06 +03:00
Petro Karashchenko
68902d8732 pid_t: unify usage of special task IDs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-22 21:22:32 +08:00
Matthew Trescott
bc80bbddc7 Add Tiva CAN driver 2022-03-15 11:32:31 -04:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Xiang Xiao
4c167b0729 Correct the code alignment 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-01 21:22:21 -03:00
Petro Karashchenko
6c2b40f98a typos: fix typos in many files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 22:10:07 +08:00
Petro Karashchenko
c7d3a674fd drivers/sensors/as5048b: fix lower half init issue 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 11:38:44 +08:00
Xiang Xiao
af72376773 fs: Remove magic field from partition_info_s 
since it is wrong and impossible to return file
system magic number from the block or mtd layer.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 09:19:52 -03:00
Xiang Xiao
71269811ca mtd: Implement BIOC_PARTINFO for all drivers 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-16 10:08:26 -03:00
Xiang Xiao
f63d1cfbbb arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-15 10:50:52 +02:00
Xiang Xiao
fad0c3b38b arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-14 11:41:59 -07:00
Xiang Xiao
6b6c11f0ad mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-12 08:01:29 -03:00
raiden00pl
2b3106fb47 Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition 
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-07 09:20:10 -03:00
Xiang Xiao
5b2a17b892 Include assert.h in necessary place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-08 13:06:08 -07:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:36:03 -07:00
Alin Jerpelea
02b244cb6f arch: arm: update licenses to Apache 
Sebastien Lorquet has submitted the CLA

Uros Platise has submitted the CLA

Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Xiang Xiao
001e7c3e76 sched: Don't include nuttx/sched.h inside sched.h 
But let nuttx/sched.h include sched.h instead to
avoid expose nuttx kernel API to userspace.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-05-24 12:11:53 +09:00
Gustavo Henrique Nihei
534c058d93 spi: Adopt CPHA as the abbreviation for clock phase 2021-05-05 16:56:07 -03:00
Xiang Xiao
3f67c67aaf arch: Fix the stack boundary calculation and check 
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-04-10 08:39:54 -07:00
Alin Jerpelea
37b314f29f LICENSE: add 3rd party license for Texas Instruments Incorporated 
Add 3rd party licenses for Texas Instruments Incorporated to the LICENSE file.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-08 22:48:46 -05:00
Alin Jerpelea
08e5378b11 NuttX: Gregory Nutt: update licenses to Apache 
Several licenses were missed in the initial work

David Sidrane has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-03 04:20:31 -07:00
Alin Jerpelea
b4a33b5ec0 NuttX: Uros Platise: update licenses to Apache 
Uros Platise has submitted the ICLA and we can migrate the licenses
 to Apache.

David Sidrane has submitted the ICLA and we can migrate the licenses
 to Apache.

Bob Feretich has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-01 12:13:12 -05:00
Alin Jerpelea
f8aed9864d NuttX: Max Holtzberg: update licenses to Apache 
Max Holtzberg has submitted the ICLA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-01 12:13:12 -05:00
Alin Jerpelea
5239764f67 arch: arm: tiva: fix Mixed case identifier errors 
fix nxstyle error for Mixed Case Identifier

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-24 23:49:48 -07:00
Alin Jerpelea
648b2669d1 arch: arm: tiva: fix nxstyle errors 
Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-24 23:49:48 -07:00
Alin Jerpelea
fa0dd46c6c arch: arm: tiva: Author Gregory Nutt: update licenses to Apache 
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-24 23:49:48 -07:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
Masayuki Ishikawa
d87f350831 arch, boards, drivers, include, sched, wireless: Change spinlock APIs. 
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
  g_irq_spin for backword compatibility (In this case, NULL must be specified)

Impact:
- None

Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-07 21:28:56 -08:00
YAMAMOTO Takashi
c10fb40322 arch/arm/src/tiva/common/tiva_i2c.c: Fix syslog formats 2020-11-30 05:28:17 -06:00
YAMAMOTO Takashi
c560c36716 arch/arm/src/tiva/common/tiva_ssi.c: Fix syslog formats 2020-11-30 05:28:17 -06:00
YAMAMOTO Takashi
e37bbd9173 arch/arm/src/tiva/common/lmxx_tm4c_gpioirq.c: Fix a syslog format 
The original code seems using "%08b" format to mean a binary
representation. I couldn't find it in the NuttX printf implementation
or standards.
 2020-11-30 05:28:17 -06:00
YAMAMOTO Takashi
ede1dcf706 arch/arm/src/tiva/common/tiva_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
Juha Niskanen
a01a01ab45 arch: spi: fix typos and run nxstyle 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2020-10-31 10:40:41 -07:00
Brennan Ashton
5e8bcaa360 serial: nxstyle fixes 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-10-20 14:43:19 +08:00
Juha Niskanen
94f0f55911 arch: serial: fix all TCGETS retrieving zero baud rate 
cfsetispeed() now stores baud rate to c_cflag member of
struct termios, so it must not be overridden later on.

Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2020-10-20 14:43:19 +08:00
Nathan Hartman
55b9f046c9 tiva: Fix nxstyle warnings 
arch/arm/src/tiva/common/lm4xx_tm3c_sysctrl.c:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/common/lmxx_tm4c_gpioirq.c:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/common/lmxx_tm4c_start.c:

    * Fix nxstyle warnings. No functional changes.
 2020-10-11 20:36:47 +01:00
Nathan Hartman
0eae2a1f59 tiva: tiva_ssi.c: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_ssi.c:

    * Fix nxstyle warnings. No functional changes.
 2020-09-15 12:48:20 -03:00
Nathan Hartman
e681396d35 tiva: tiva_lowputc.c, tiva_qencoder.c: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_lowputc.c:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/common/tiva_qencoder.c:

    * Fix nxstyle warnings. No functional changes.
 2020-09-14 12:16:28 -03:00
Nathan Hartman
1ab683387d tiva: tiva_eeprom.c: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_eeprom.c:

    * Fix nxstyle warnings. No functional changes.
 2020-09-13 13:11:26 -03:00
Nathan Hartman
70caa27c4c tiva: tiva_dumpgpio.c: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_dumpgpio.c:

    * Fix nxstyle warnings. No functional changes.
 2020-09-12 00:38:37 +08:00
Nathan Hartman
3316c196d4 tiva: tiva_adclow.c, tiva_allocateheap: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_adclow.c:

    * Fix nxstyle warnings. No functional changes.

arch/arm/src/tiva/common/tiva_allocateheap.c

    * Fix nxstyle warnings. No functional changes.
 2020-09-10 23:54:17 +08:00
Ouss4
06ca12e6b9 arch/: Trivial typos, mostly "their is" to "there is" 2020-09-09 14:09:43 -04:00
Nathan Hartman
8f6b2f6948 tiva: tiva_adclib.c: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_adclib.c:

    * Fix nxstyle warnings. No functional changes.
 2020-09-09 08:35:19 -07:00
barbiani
20c5c57cf6 Update tiva_timerlow32.c 
Missing callback argument field.
 2020-09-09 08:34:26 -07:00
Nathan Hartman
835d394856 tiva: tiva_timerlow32.c: Fix nxstyle warnings 
arch/arm/src/tiva/common/tiva_timerlow32.c:

    * Fix nxstyle warnings. No functional changes.
 2020-09-08 23:38:09 +08:00
Masayuki Ishikawa
36c1f7ccf0 arch: tiva: Introduce tiva_idle.c 2020-05-24 09:44:46 -03:00
Gregory Nutt
a569006fd8 sched/: Make more naming consistent 
Rename various functions per the quidelines of https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions

    nxsem_setprotocol -> nxsem_set_protocol
    nxsem_getprotocol -> nxsem_get_protocol
    nxsem_getvalue -> nxsem_get_value
 2020-05-17 14:01:00 -03:00
Xiang Xiao
517974787f Rename clock_systime[r|spec] to clock_systime_[ticks|timespec] 
follow up the new naming convention:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions
 2020-05-10 14:35:50 -06:00
Gregory Nutt
673640b313 Run all .c and .h modified by this PR through nxstyle 
The are remaining nxstyle complaints due to the use of mixed case identifiers in arch/arm/src/lc823450/lc823450_irq.c This, cannot be easily fixed since it depends on register definitions in header files that have implications to section other lc823450 files.
 2020-05-01 16:55:33 -03:00