Summary:
Adding virtual evaluate platform FVP. This FVP board configuration
will be used to emulate generic ARM64v8-R (Cotex-R82)series hardware
platform and provide support for these devices:
- GICv3 interrupt controllers for ARMv8-r
- PL011 UART controller(FVP)
Note:
1. ostest is PASSED at fvp ( single core and SMP)
2. the FVP tools can be download from ARM site, please check FVP
board readme.txt
TODO: merge PL011 UART driver to common place
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
For ARM64 architecture, the arch timer is 64-bit,
the CONFIG_SYSTEM_TIME64 need to be enabled just like
x86_64 and risc-v 64
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
The aarch64 have EL0~El3 execute level and NS/S (security state),
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement up_earlyserialinit and
up_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
The original code hard-coded card detection to the low when card is
inserted and high when not. This might not be true on every board
because it depends on the slot and wiring used. The second reason is
because it is also possible to detect card with D3 pin pull-up when the
slot does not provide dedicated card detection switch.
This introduces new argument to the sam_hsmci_initialize to allow
invert of card detection pin. It also applies this invert to existing
boards as that was the state up to this point.
This commit adds configuration file with enabled MCAN support. This is
mainly to track changes in architectural driver that could cause build
errors.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit updates configuration pikron-bb (configuration for open
hardware experimental board) to support permanent magnet sychnronous
motor control. This includes setup of PWM, GPIO and ADC peripherals.
Required follow up changes are done to pinout definition.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Summary:
- Fix knsh/defconfig to work with pyOCD
- Fix kernel-space.ld to boot
- Fix memory.ld for CONFIG_BUILD_PROTECTED=y
Impact:
- CONFIB_BUILD_PROTECTED=y only
Testing:
- Tested with imxrt1060-evk
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
First decoupling changes related to CMAKE
BINDIR/APPSBINDIR:
Output path of Kconfig which dynamically generated by NuttX Kernel/Apps
This option is consistent with the TOPDIR/APPSDIR by default, and will
be changed when out-of-tree compilation is supported
Signed-off-by: chao an <anchao@xiaomi.com>
Fixing an issue that occurred When building with the
Sourcery CodeBench Lite MIPS Toolchain for Linux
(CONFIG_MIPS32_TOOLCHAIN_SOURCERY_CODEBENCH_LITE).
There is currently a big problem in the address environment handling which
is that the address environment is released too soon when the process is
exiting. The current MMU mappings will always be the exiting process's, which means
the system needs them AT LEAST until the next context switch happens. If
the next thread is a kernel thread, the address environment is needed for
longer.
Kernel threads "lend" the address environment of the previous user process.
This is beneficial in two ways:
- The kernel processes do not need an allocated address environment
- When a context switch happens from user -> kernel or kernel -> kernel,
the TLB does not need to be flushed. This must be done only when
changing to a different user address environment.
Another issue is when a new process is created; the address environment
of the new process must be temporarily instantiated by up_addrenv_select().
However, the system scheduler does not know that the process has a different
address environment to its own and when / if a context restore happens, the
wrong MMU page directory is restored and the process will either crash or
do something horribly wrong.
The following changes are needed to fix the issues:
- Add mm_curr which is the current address environment of the process
- Add a reference counter to safeguard the address environment
- Whenever an address environment is mapped to MMU, its reference counter
is incremented
- Whenever and address environment is unmapped from MMU, its reference
counter is decremented, and tested. If no more references -> drop the
address environment and release the memory as well
- To limit the context switch delay, the address environment is freed in
a separate low priority clean-up thread (LPWORK)
- When a process temporarily instantiates another process's address
environment, the scheduler will now know of this and will restore the
correct mappings to MMU
Why is this not causing more noticeable issues ? The problem only happens
under the aforementioned special conditions, and if a context switch or
IRQ occurs during this time.
The cyw43-driver is a submodule in the pick-sdk, if the submodule is
not updated, the dummy firmware driver will be used, update the document
to correct the setup flow.
${PICO_SDK_PATH}/lib/cyw43-driver/firmware/43439A0-7.95.49.00.combined
Signed-off-by: chao an <anchao@xiaomi.com>
Summary:
- Since QEMU does not report L2CC information correctly,
NuttX stops if DEBUG_ASSERTIONS=y.
- This commit adds DEBUG_ASSERTIONS=y to citest/defconfigs
and disables L2CC related configs.
- Also, it disables RAMLOG to show the crash information
Impact:
- None
Testing:
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
PWM driver for multiple peripherals supplied in gateware.
Only single channel frequency and duty cycle control is implemented. Pulse counting and multichannel features are not currently feasible.
Additions also include a new board configuration for arty-a7 which enables the PWM driver and example application.
continue the follow work:
commit 43e7b13697
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Sun Jan 22 19:31:32 2023 +0800
assert: Log the assertion expression in case of fail
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
These are basically the same from the esp32-devkitc board. As the
defconfigs do not make use of any board-specific peripheral, there
is no need to duplicate them in every ESP32 board.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
MCUboot support is no longer behind EXPERIMENTAL for the following
chips:
- ESP32
- ESP32-S2
- ESP32-S3
- ESP32-C3
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Summary:
- This commit adjusts TCP and UDP configurations based on
sabre-6quad/configs/netnsh/defconfig
Impact:
- sabre-6quad only
Testing:
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This PR adds the existing Goodix GT9XX Touch Panel Driver to the Bringup Function for PINE64 PinePhone.
With this PR, LVGL Touchscreen Apps will respond to Touch Input on PinePhone.
### Modified Files
`boards/arm64/a64/pinephone/src/pinephone_bringup.c`: Added GT9XX Touch Panel Driver to PinePhone Bringup Function
`boards/arm64/a64/pinephone/src/Makefile`: Added `pinephone_touch.c` to the Makefile
`include/nuttx/input/gt9xx.h`: Fixed a comment in GT9XX Touch Panel Driver
### New Files
`boards/arm64/a64/pinephone/src/pinephone_touch.c`, `pinephone_touch.h`: Register GT9XX Touch Panel Driver on PinePhone
`boards/arm64/a64/pinephone/configs/lvgl/defconfig`: Added PinePhone Board Config `lvgl` to support LVGL Touchscreen Apps
### Updated Documentation
`Documentation/platforms/arm/a64/boards/pinephone/index.rst`: Added PinePhone Board Config `lvgl` for LVGL Touchscreen Apps
Summary:
- This commit adds knetnsh64 and knetnsh64_smp
Impact:
- None
Testing:
- Tested with ping, telnet and iperf on QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Move `SIM_I2CBUS_ID` and `SIM_SPIDEV_NAME` from board to arch.
This allows you not to rely on board configuration.
Signed-off-by: xinbingnan <xinbingnan@xiaomi.com>
1. Change IP address format to addr/prefix, to be compatible with both IPv4/IPv6.
- When adding address in CIDR type, netmask/route will be automatically added.
2. Since route of whole subnet is added automatically, not specifying NuttX's IP any more.
- Multiple NuttX simulators (with IP 10.0.1.x) attached to same bridge can surf the net at same time.
3. NAT66 is used to make sure it works even if host has only one IPv6 address.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
