Commit Graph

43985 Commits

Author SHA1 Message Date
YAMAMOTO Takashi
ebbfa034c7 libs/libc/libc.csv: Add shutdown 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
a06cf25ab6 libs/libc/libc.csv: Add getaddrinfo and friends 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
1b7cb3ef63 libs/libc/libc.csv: Add dlfcn functions 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
f5fb4d4d98 libs/libc/libc.csv: Add strtoumax and strtoimax 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
0b8464419d libs/libc/libc.csv: Add ctype functions 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
ead9bf6481 libs/libc/libc.csv: Add ferror 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
c22e8c5427 libs/libc/libc.csv: Add rewind 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
c46bae4a4f libs/libc/libc.csv: Add _assert 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
26b077080b libs/libc/libc.csv: Add __stack_chk_fail 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
79b608ab19 add ssp.h 2022-01-29 01:04:23 +08:00
YAMAMOTO Takashi
b9e73ed8ba libs/libc/libc.csv: Add mallinfo and malloc_size 2022-01-29 01:04:23 +08:00
chao.an
7d8c2c1ad6 cortex-m/doirq: do not update the CURRENT_REGS on nested interrupt handling
current implementation incorrectly update CURRENT_REGS to interrupt context if
trigger nested interrupt, (e.g, hard fault occurs during interrupt handling)
this would ambiguous for programs using CURRENT_REGS, this patch will prohibit
the update of CURRENT_REGS on nested interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-29 01:04:00 +08:00
ligd
d8c2610157 idle: remove heap & stack check in idle thread
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-01-29 00:53:47 +08:00
ligd
b316611ef0 Revert "sem: remove limitation of irq context when do sem_trywait"
This reverts commit 7c547b3ebd.
2022-01-29 00:53:47 +08:00
Xiang Xiao
1c2c0e4707 arch/Toolchain.defs: Simplify the builtin library addition for EXTRA_LIBS
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-28 12:02:38 +01:00
Alexander Lunev
b2f3cefe3d sim/netdev,tapdev: implemented emulation of TX done and RX ready interrupts
and removed two tcp_send_txnotify() calls from tcp_sendfile (they are not needed anymore).

As a result, the TX throughput of both the tcp_send_buffered and tcp_send_unbuffered
is significantly boosted in case of TUN/TAP network device.
2022-01-28 18:16:42 +08:00
YAMAMOTO Takashi
e596d5bd5e binfmt/libelf: Implement sh_addralign handling
Basically, mirror the following two commits from modlib.
It's shame we have two copies of elf loaders.

```
commit 51490bad55
Author: YAMAMOTO Takashi <yamamoto@midokura.com>
Date:   Wed Apr 14 17:07:39 2021 +0900

    modlib: Implement sh_addralign handling

    I've seen a module with 16 bytes .rodata alignment for xmm operations.
    It was getting SEGV on sim/Linux because of the alignment issue.
    The same module binary seems working fine after applying this patch.

    Also, tested on sim/macOS and esp32 on qemu,
    using a module with an artificially large alignment. (64 bytes)
```

```
commit 418e11b8b3
Author: YAMAMOTO Takashi <yamamoto@midokura.com>
Date:   Thu Apr 15 11:33:48 2021 +0900

    modlib: Always use separate allocation for text and data

    Pros:

    * Reduce code differences
    * Smaller allocations for !CONFIG_ARCH_USE_MODULE_TEXT

    Cons:

    * Likely to use more memory for !CONFIG_ARCH_USE_MODULE_TEXT in total

    Tested with:

    * sim:module on macOS
    * esp32-devkit:nsh + CONFIG_MODULE on qemu
    * lm3s6965-ek:qemu-protected + CONFIG_EXAMPLES_SOTEST on qemu
```
2022-01-28 16:23:23 +08:00
liucheng5
764fc7ef5e fix: sensor: ppg of dual- and quad-channel sensor types
Some PPG devices have 4 ADCs to output quad-channel PPG values while some of them only have 2 ADCs to output dual-channel PPG.
To deal the case above, the type PPGD(PPG of Dual-channel) takes the place of former type PPG, which also have 2-channel PPG outputs. Type PPGQ (PPG of Quad-channel) is new for 4-ADC-PPG. Both types have contained new data "gain" to indicate ADC gains of each PPG channel, for the reason that the gains may vary during automatical optical adjustments.

Signed-off-by: liucheng5 <liucheng5@xiaomi.com>
2022-01-28 14:07:46 +08:00
Gustavo Henrique Nihei
b0d24f53c4 xtensa: Add initial support for ESP32-S3
Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-27 13:46:50 -03:00
Fotis Panagiotopoulos
f8ba016d72 sim: Added Kconfig option for UART buffer size. 2022-01-27 17:15:17 +01:00
Petro Karashchenko
7b5af90565 tools/mkromfsimg.sh: add attribute to set minimum 4 bytes aignment for romfs image data
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-27 23:50:47 +08:00
Ville Juven
7c116efe05 Add support for a ROMFS image for MPFS
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h

The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
2022-01-27 11:06:43 -03:00
Gustavo Henrique Nihei
281ec4682f docker/linux: Add ESP32-S3 toolchain and binaries
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-27 10:01:17 -03:00
Petro Karashchenko
0ffffe19b1 typo: change evernt to event in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-27 09:57:31 -03:00
zhuyanlin
6578461cc8 tcbinfo: add packet align to struct tcbinfo
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 17:36:27 +08:00
zhuyanlin
8f1c6ee7bc tools/jlink-nuttx: update tcbinfo follow nuttx arch tcbinfo_s
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 17:36:27 +08:00
Xiang Xiao
f903a55102 sched/tcbinfo: Fix the compile warning
Update tcbinfo struct

armv8-m/arm_tcbinfo.c:109:3: warning: excess elements in struct initializer
  109 |   TCB_REG_OFF(REG_S31),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:109:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:110:3: warning: excess elements in struct initializer
  110 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:110:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:111:3: warning: excess elements in struct initializer
  111 |   TCB_REG_OFF(REG_FPSCR),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:111:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:112:3: warning: excess elements in struct initializer
  112 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:112:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:37:1: warning: missing braces around initializer [-Wmissing-braces]
   37 | {

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 17:36:27 +08:00
YAMAMOTO Takashi
dad4a7f8f7 symtab_findbyvalue: just retun NULL for NULL symtab 2022-01-27 10:23:37 +01:00
YAMAMOTO Takashi
0edb290951 symtab_findbyname: just retun NULL for NULL symtab
The condition is not fatal at all.
It's better to let the caller handle the failure.
2022-01-27 10:23:37 +01:00
Ville Juven
4bd1bd177b RISC-V MMU: Add missing implementation for PTE getter
For some reason this was (mistakenly) left out from the patch
that was supposed to have it.
2022-01-27 10:22:30 +01:00
zhuyanlin
644c2be3aa armv7-a/r:cache: implemention clean&flush_dcache_all
For armv7-a/r cache:
And clean_dcache_all, flush_dcache_all

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
zhuyanlin
1b08f607be arm/xtensa:cache: flush/clean dcache all if size large than cache size
For performance, if size large than cache size, use xxx_all instead

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
zhuyanlin
4d5c2586a9 armv7-a/r:cp15_invalidate_dcache_all: fix Sets mask error.
As NumSets field is bits 13-27, use 0x7fff instead.
And add way to get from CCSIDR.
2022-01-27 15:13:08 +08:00
Huang Qi
0c28fe9831 boards: Remove unused NXFLAT flags from Make.defs
Since NXFLAT only avaliable on arm.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-27 11:08:43 +08:00
YAMAMOTO Takashi
fd58398918 binfmt/elf.c: Fix syslog formats for ELF64
Loosely followed the copy in mod_insmod.c.
2022-01-27 10:57:48 +08:00
Alexander Lunev
c45534f41b tools/nxstyle: fixed "Mixed case identifier found" errors related to sim/wpcap 2022-01-27 10:37:32 +08:00
chao.an
e518a9f031 tools/Config.mk: suppress all normal output for cmp
Fix build break:
make: *** No rule to make target 'byte', needed by 'differ'.  Stop.

Regression by:
-----------------------------------------------------
|commit 0951f70df6
|
|    Improve dependencies for include/nuttx/version.h
-----------------------------------------------------

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-26 14:45:32 +01:00
Petro Karashchenko
311efcd180 arch/z80: fix garbage collector option to linker
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-26 16:50:59 +08:00
Alexander Lunev
2a6de301ee net/tcp: transformed NET_TCP_FAST_RETRANSMIT_WATERMARK option to boolean.
According to RFC 5681 (3.2) the TCP Fast Retransmit algorithm should start
if the threshold of 3 duplicate ACKs is reached.
Thus the threshold should be a constant, not an integer option.
2022-01-26 11:50:48 +08:00
Xiang Xiao
ecccc614bd arch: Add up_perf_getfreq function
it's important to know the perf count frequency

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-25 21:02:14 -03:00
Alexander Lunev
8be9cb9f72 net/tcp/sendfile: notify the device driver of the availability of TX data on TCP retransmission
(as well as on sending normal TCP packets).
2022-01-26 02:01:25 +08:00
Alexander Lunev
7e748e63dd net/tcp/tcp_sendfile: optimized out sendfile_txnotify() function 2022-01-26 02:01:06 +08:00
Huang Qi
4b6ca9432b board/Board.mk: Make romfs_img 4 byte aligned
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-25 14:49:12 +01:00
Xiang Xiao
bc2dd37051 drivers/timers: Add weak_function for up_ function
so the user could replace the implementation if need

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-25 13:35:05 +01:00
chao.an
e781787cb9 sched/critmonitor: remove the assertion if counter == 0
Perf timer interface generally uses the hardware cycle counter
provided by the arch chip directly(such as DWT_CYCCNT(cortex-m)),
CYCCNT is a free running counter and counting upwards.
It wraps around to 0 on overflow.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-25 20:24:58 +08:00
Petro Karashchenko
48211f90d3 ci: select ARMV7A_TOOLCHAIN_GNU_EABIL for ARMv7-A based builds
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-25 20:24:28 +08:00
Ville Juven
fc3cd308d5 Wipe the PMP configuration in MPFS bootloader start routine
This way old PMP configurations are removed upon warm reset.
2022-01-25 20:22:34 +08:00
Ville Juven
81188d9c94 Extend the RISC-V PMP functionality
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
 - The function goes through every PMP entry and tests if an address
   range from [base, base+size] has been configured for desired
   access rights.
 - If several PMP entries match the range and access rights, the
   information is combined
 - End result is either no access, a partial match was found, or a full
   match was found. Details about the partial match are not provided.

The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
2022-01-25 20:22:34 +08:00
Ville Juven
8a4881c4e5 Implement CONFIG_BUILD_PROTECTED with MMU
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW

This frees the PMP for other use, e.g. HART memory separation.

The page tables are statically allocated, 1 per level.

This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).

If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.

A more flexible solution for PMP configuration will follow.
2022-01-25 20:22:34 +08:00
Ville Juven
7eb726d57f Add proper user/kernel space linker scripts for knsh target
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.

Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
2022-01-25 20:22:34 +08:00