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a1x
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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am335x
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arch/arm/include/amm335x: Trivial, cosmetic changes after review
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2019-01-08 08:15:04 -06:00 |
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arm
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Squashed commit of the following:
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2019-04-29 14:52:05 -06:00 |
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armv6-m
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Squashed commit of the following:
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2019-04-29 14:52:05 -06:00 |
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armv7-a
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Squashed commit of the following:
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2019-04-29 14:52:05 -06:00 |
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armv7-m
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This commit removes CONFIG_ARCH_INT_DISABLEALL. In the normal course of things, interrupts must occasionally be disabled using the up_irq_save() inline function to prevent contention in use of resources that may be shared between interrupt level and non-interrupt level logic. Now the question arises, if we are using BASEPRI to disable interrupts and have high priority interrupts enabled (CONFIG_ARCH_HIPRI_INTERRUPT=y), do we disable all interrupts except SVCall (we cannot disable SVCall interrupts). Or do we only disable the "normal" interrupts?
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2019-08-09 10:52:35 -06:00 |
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armv7-r
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Squashed commit of the following:
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2019-04-29 14:52:05 -06:00 |
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c5471
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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cxd56xx
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arch/arm/include/cxd56xx/chip.h: The correction of commit c300f27130 must be applied to the CXD56xx too.
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2019-08-10 08:33:47 -06:00 |
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dm320
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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efm32
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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imx1
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i.MX6: Add IRQ header file
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2016-02-28 14:07:53 -06:00 |
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imx6
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Fix lots of typos in C comments and Kconfig help text
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2018-07-08 18:24:45 -06:00 |
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imxrt
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Merged imxrt1020 into master
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2019-04-30 16:08:46 -06:00 |
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kinetis
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Merged in dagar/nuttx/pr-kinetic_minor_fix (pull request #820)
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2019-01-19 15:39:46 +00:00 |
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kl
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arch/: Clean up some naming and spacing.
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2018-06-20 15:38:06 -06:00 |
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lc823450
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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lpc17xx_40xx
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Merged in jjlange/nuttx/lpc40xx (pull request #946)
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2019-07-11 16:50:00 +00:00 |
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lpc31xx
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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lpc43xx
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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lpc54xx
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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lpc214x
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Fix names of pre-processor variables used in header file idempotence
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2016-08-06 18:48:45 -06:00 |
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lpc2378
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Fix names of pre-processor variables used in header file idempotence
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2016-08-06 18:48:45 -06:00 |
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max326xx
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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moxart
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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nrf52
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arch/arm/include/nrf52/ and arch/arm/src/nrf52: 1. Added 52840 family support 2. Use common irq and memory layout header file for 52832 & 52840.
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2019-03-12 09:43:49 -06:00 |
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nuc1xx
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Cosmetic changes to spacing and comments.
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2017-04-20 14:08:08 -06:00 |
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s32k1xx
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This commit brings the initial files for a port to the NXP S32K1xx family. This is very much a work in progress and is little more that a partial configuration/build environment and some S32K1xx register definition header files
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2019-08-12 12:12:58 -06:00 |
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sam34
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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sama5
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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samd2l2
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Rename all usage of samdl/SAMDL to samd2l2/SAMD2L2 to make room in the name space for the forthcoming samd5e5/SAMD5E5
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2018-07-22 15:54:12 -06:00 |
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samd5e5
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configs/metro-m4: Fix RxD interrupt pin selection. The number SERCOM interrupts do not refer to PAD numbers, but to bit positions in the INFLAG register (very tiny footnote in the data sheet). With with final fix, the basic NSH configuration appears fully functional.
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2018-09-01 15:29:22 -06:00 |
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samv7
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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stm32
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Merged in raiden00/nuttx_pe (pull request #796)
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2019-01-02 12:12:28 +00:00 |
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stm32f0l0g0
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Rename STM32F0L0 to STM32F0L0G0 since it now alsow supports the STM32G0 thanks to Mateusz Szafoni's contribution
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2019-05-27 08:16:24 -06:00 |
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stm32f7
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*Merged in zhoukejun/nuttx_nucleo-f767zi (pull request #838)
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2019-03-11 03:44:57 +00:00 |
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stm32h7
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arch/arm/src/stm32h7/: Add stm32h7 ethernet driver. This is the initial push for the ethernet driver. The driver has been tested to be working on a nucleo board. This is still WIP, it doesn't for example do MAC filtering on HW level, but just receives all ethernet packets.
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2019-04-30 08:43:39 -06:00 |
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stm32l4
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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str71x
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Clean up and review of header files for conformance to standards
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2015-06-12 19:26:01 -06:00 |
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tiva
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arch/arm/src/tiva: LM3S, LM4F, TM4C: Fix GPIO IRQ error, ports R, S, T. Preprocessor logic for CONFIG_TIVA_GPIOx_IRQS was setting/clearing port Q defines when it should act on ports R, S, T. gpioport2irq() was missing handling for port T.
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2019-08-04 16:55:26 -06:00 |
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tms570
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arch/arm/include/tms570, arm/src/armv7-r, and arm/src/tms570: Adds support for the TMS570LS3137ZWT and corrects seversl ARMv7-R and TMS570 issues
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2018-04-18 08:58:36 -06:00 |
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xmc4
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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.gitignore
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Move LPC17xx IOCON register definitions from lpc17_gpio.h to lpc17_iocon.h; fix a few more .gitignore files
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2013-04-04 18:12:44 -06:00 |
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arch.h
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Standardize the width of all comment boxes in header files
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2015-10-02 17:42:29 -06:00 |
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elf.h
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arch/arm/include/syscall.h: Add missing inclusion of arch/armv7-r/syscall.h for CortexR.
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2019-01-26 07:43:31 -06:00 |
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inttypes.h
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Add architecture-specific inttypes.h
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2016-10-27 16:01:38 -04:00 |
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irq.h
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arch/arm: Add the initial cortex-a7 archtiecture support
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2019-03-19 11:51:29 -06:00 |
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limits.h
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Make some file section headers more consistent with standard
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2015-04-08 08:04:12 -06:00 |
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setjmp.h
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arch/arm/src/armv7-m: Add ARMv7-M setjmp/longjump functions.
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2019-08-06 15:59:19 -06:00 |
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spinlock.h
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arch/arm: Add the initial cortex-a7 archtiecture support
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2019-03-19 11:51:29 -06:00 |
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stdarg.h
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Add a generic GCC stdarg.h header file
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2012-07-08 14:50:43 +00:00 |
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syscall.h
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arch/arm: Add the initial cortex-a7 archtiecture support
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2019-03-19 11:51:29 -06:00 |
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tls.h
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TLS: Forgot to add a file before last commit
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2016-03-11 12:30:04 -06:00 |
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types.h
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Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()
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2016-02-14 16:11:25 -06:00 |
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