nuttx/arch/risc-v/Kconfig

#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_RISCV
comment "RISC-V Options"

choice
	prompt "RISC-V chip selection"
	default ARCH_CHIP_RISCV_CUSTOM

config ARCH_CHIP_FE310
	bool "SiFive FE310"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ONESHOT
	select ALARM_ARCH
	---help---
		SiFive FE310 processor (E31 RISC-V Core with MAC extensions).

config ARCH_CHIP_K210
	bool "Kendryte K210"
	select ARCH_RV64
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_HAVE_FPU if !K210_WITH_QEMU
	select ARCH_HAVE_DPFPU if !K210_WITH_QEMU
	select ARCH_HAVE_MPU
	select ARCH_HAVE_TESTSET
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_MISALIGN_EXCEPTION
	select ONESHOT
	select ALARM_ARCH
	---help---
		Kendryte K210 processor (RISC-V 64bit core with GC extensions)

config ARCH_CHIP_LITEX
	bool "Enjoy Digital LITEX VEXRISCV"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_DCACHE
	select ARCH_HAVE_TICKLESS
	select ARCH_HAVE_RESET
	select LIBC_FDT
	select DEVICE_TREE
	---help---
		Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).

config ARCH_CHIP_BL602
	bool "BouffaloLab BL602"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_HAVE_FPU
	select ARCH_HAVE_RESET
	select ARCH_HAVE_MISALIGN_EXCEPTION
	select ONESHOT
	select ALARM_ARCH
	---help---
		BouffaloLab BL602(rv32imfc)

config ARCH_CHIP_ESP32C3
	bool "Espressif ESP32-C3"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_C
	select ARCH_VECNOTIRQ
	select ARCH_HAVE_MPU
	select ARCH_HAVE_RESET
	select LIBC_ARCH_MEMCPY
	select LIBC_ARCH_MEMCHR
	select LIBC_ARCH_MEMCMP
	select LIBC_ARCH_MEMMOVE
	select LIBC_ARCH_MEMSET
	select LIBC_ARCH_STRCHR
	select LIBC_ARCH_STRCMP
	select LIBC_ARCH_STRCPY
	select LIBC_ARCH_STRLCPY
	select LIBC_ARCH_STRNCPY
	select LIBC_ARCH_STRLEN
	select LIBC_ARCH_STRNLEN
	select ARCH_HAVE_TEXT_HEAP
	select ARCH_HAVE_BOOTLOADER
	select ARCH_HAVE_PERF_EVENTS
	select ARCH_HAVE_DEBUG
	---help---
		Espressif ESP32-C3 (RV32IMC).

config ARCH_CHIP_ESP32C3_GENERIC
	bool "ESP32-C3"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_C
	select ARCH_VECNOTIRQ
	select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
	select ARCH_HAVE_MPU
	select ARCH_HAVE_RESET
	select ARCH_HAVE_RNG
	select ARCH_HAVE_TICKLESS
	select LIBC_ARCH_ATOMIC
	select LIBC_ARCH_MEMCPY
	select LIBC_ARCH_MEMCHR
	select LIBC_ARCH_MEMCMP
	select LIBC_ARCH_MEMMOVE
	select LIBC_ARCH_MEMSET
	select LIBC_ARCH_STRCHR
	select LIBC_ARCH_STRCMP
	select LIBC_ARCH_STRCPY
	select LIBC_ARCH_STRLCPY
	select LIBC_ARCH_STRNCPY
	select LIBC_ARCH_STRLEN
	select LIBC_ARCH_STRNLEN
	select ESPRESSIF_SOC_RTC_MEM_SUPPORTED
	select ARCH_CHIP_ESPRESSIF
	select ARCH_HAVE_DEBUG
	---help---
		ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory

config ARCH_CHIP_ESP32C6
	bool "ESP32-C6"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_VECNOTIRQ
	select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
	select ARCH_HAVE_MPU
	select ARCH_HAVE_RESET
	select ARCH_HAVE_RNG
	select ARCH_HAVE_TICKLESS
	select LIBC_ARCH_MEMCPY
	select LIBC_ARCH_MEMCHR
	select LIBC_ARCH_MEMCMP
	select LIBC_ARCH_MEMMOVE
	select LIBC_ARCH_MEMSET
	select LIBC_ARCH_STRCHR
	select LIBC_ARCH_STRCMP
	select LIBC_ARCH_STRCPY
	select LIBC_ARCH_STRLCPY
	select LIBC_ARCH_STRNCPY
	select LIBC_ARCH_STRLEN
	select LIBC_ARCH_STRNLEN
	select ESPRESSIF_SOC_RTC_MEM_SUPPORTED
	select ARCH_CHIP_ESPRESSIF
	---help---
		Espressif ESP32-C6 (RV32IMAC).

config ARCH_CHIP_ESP32H2
	bool "ESP32-H2"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_C
	select ARCH_VECNOTIRQ
	select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
	select ARCH_HAVE_MPU
	select ARCH_HAVE_RESET
	select ARCH_HAVE_RNG
	select ARCH_HAVE_TICKLESS
	select LIBC_ARCH_ATOMIC
	select LIBC_ARCH_MEMCPY
	select LIBC_ARCH_MEMCHR
	select LIBC_ARCH_MEMCMP
	select LIBC_ARCH_MEMMOVE
	select LIBC_ARCH_MEMSET
	select LIBC_ARCH_STRCHR
	select LIBC_ARCH_STRCMP
	select LIBC_ARCH_STRCPY
	select LIBC_ARCH_STRLCPY
	select LIBC_ARCH_STRNCPY
	select LIBC_ARCH_STRLEN
	select LIBC_ARCH_STRNLEN
	select ESPRESSIF_ESPTOOLPY_NO_STUB
	select ESPRESSIF_SOC_RTC_MEM_SUPPORTED
	select ARCH_CHIP_ESPRESSIF
	---help---
		Espressif ESP32-H2 (RV32IMC).

config ARCH_CHIP_C906
	bool "THEAD C906"
	select ARCH_RV64
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU
	select ARCH_HAVE_MPU
	select ONESHOT
	select ALARM_ARCH
	---help---
		THEAD C906 processor (RISC-V 64bit core with GCVX extensions).

config ARCH_CHIP_MPFS
	bool "MicroChip Polarfire (MPFS)"
	select ARCH_RV64
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU
	select ARCH_HAVE_MPU
	select ARCH_MMU_TYPE_SV39
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	select ARCH_HAVE_RESET
	select ARCH_HAVE_SPI_CS_CONTROL
	select ARCH_HAVE_PWM_MULTICHAN
	select ARCH_HAVE_S_MODE
	select ONESHOT
	select ALARM_ARCH
	---help---
		MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).

config ARCH_CHIP_RV32M1
	bool "NXP RV32M1"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_C
	---help---
		NXP RV32M1 processor (RISC-V Core with PULP extensions).

config ARCH_CHIP_QEMU_RV
	bool "QEMU RV"
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_MPU
	select ARCH_MMU_TYPE_SV39 if ARCH_CHIP_QEMU_RV64
	select ARCH_MMU_TYPE_SV32 if ARCH_CHIP_QEMU_RV32
	select NUTTSBI_LATE_INIT if NUTTSBI
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	select ARCH_HAVE_S_MODE
	select ARCH_HAVE_ELF_EXECUTABLE
	select ONESHOT
	select ALARM_ARCH
	select ARCH_HAVE_DEBUG
	---help---
		QEMU Generic RV32/RV64 processor

config ARCH_CHIP_HPM6000
	bool "Hpmicro HPM6000"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ONESHOT
	select ALARM_ARCH
	---help---
		Hpmicro HPM6000 processor (D45 RISC-V Core with MAC extensions).

config ARCH_CHIP_HPM6750
	bool "Hpmicro HPM6750"
	select ARCH_RV32
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ONESHOT
	select ALARM_ARCH
	---help---
		Hpmicro HPM6750 processor (D45 RISC-V Core with MAC extensions).

config ARCH_CHIP_JH7110
	bool "StarFive JH7110"
	select ARCH_RV64
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_MPU
	select ARCH_MMU_TYPE_SV39
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	select ARCH_HAVE_S_MODE
	select ONESHOT
	select ALARM_ARCH
	---help---
		StarFive JH7110 SoC.

config ARCH_CHIP_BL808
	bool "Bouffalo Lab BL808"
	select ARCH_RV64
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_MPU
	select ARCH_MMU_TYPE_SV39
	select ARCH_MMU_EXT_THEAD
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	select ARCH_HAVE_S_MODE
	select ONESHOT
	select ALARM_ARCH
	---help---
		Bouffalo Lab BL808 SoC.

config ARCH_CHIP_K230
	bool "Kendryte K230"
	select ARCH_RV64
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU
	select ARCH_HAVE_MISALIGN_EXCEPTION
	select ARCH_HAVE_MPU
	select ARCH_HAVE_ADDRENV
	select ARCH_HAVE_RESET
	select ARCH_HAVE_S_MODE
	select ARCH_HAVE_ELF_EXECUTABLE
	select ARCH_MMU_TYPE_SV39
	select ARCH_NEED_ADDRENV_MAPPING
	select NUTTSBI_LATE_INIT if NUTTSBI
	select ONESHOT
	select ALARM_ARCH
	---help---
		Kendryte K230 SoC (RV64GCV and RV64GCVX C908 cores).

config ARCH_CHIP_SG2000
	bool "SOPHGO SG2000"
	select ARCH_RV64
	select ARCH_RV_ISA_M
	select ARCH_RV_ISA_A
	select ARCH_RV_ISA_C
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_MPU
	select ARCH_MMU_TYPE_SV39
	select ARCH_MMU_EXT_THEAD
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	select ARCH_HAVE_S_MODE
	select ONESHOT
	select ALARM_ARCH
	---help---
		SOPHGO SG2000 SoC.

config ARCH_CHIP_RISCV_CUSTOM
	bool "Custom RISC-V chip"
	select ARCH_CHIP_CUSTOM
	---help---
		Select this option if there is no directory for the chip under arch/risc-v/src/.

endchoice # RISC-V chip selection

config ARCH_RV32
	bool
	default n

config ARCH_RV64
	bool
	default n
	select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF && !ARCH_RV64ILP32

config ARCH_RV64ILP32
	bool
	depends on ARCH_RV64
	default n

config ARCH_RV_ISA_M
	bool
	default n

config ARCH_RV_ISA_A
	bool
	default n
	select ARCH_HAVE_TESTSET

config ARCH_RV_ISA_C
	bool
	default n

config ARCH_RV_ISA_V
	bool
	default n
	depends on ARCH_FPU

if ARCH_RV_ISA_V

config ARCH_RV_VECTOR_BYTE_LENGTH
	int "Vector Register Length in bytes"
	default 32
	---help---
		Predefined vector register length. If CSR vlenb is greater than the
		current reserved value, appropriate memory will be allocated to
		save/restore the vector registers.
		The XLEN-bit-wide read-only CSR vlenb holds the value VLEN/8, i.e.,
		the vector register length in bytes.  The value in vlenb is a
		design-time constant in any implementation.  Without this CSR, several
		instructions are needed to calculate VLEN in bytes. The code has to
		disturb current vl and vtype settings which require them to be saved and restored.

endif

config ARCH_RV_ISA_ZICSR_ZIFENCEI
	bool
	default y
	---help---
		https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
		https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd
		GCC-12.1.0 bumped the default ISA spec to the newer 20191213 version,
		which moves some instructions from the I extension to the Zicsr and
		Zifencei extensions. This requires explicitly specifying Zicsr and
		Zifencei when GCC >= 12.1.0. To make life easier, and avoid forcing
		toolchains that default to a newer ISA spec to version 2.2. For
		clang < 17 or GCC < 11.3.0, for which this is not possible or need
		special treatment.

config ARCH_RV_EXPERIMENTAL_EXTENSIONS
	string "LLVM RISC-V Experimental Extensions"
	default ""
	depends on RISCV_TOOLCHAIN_CLANG
	---help---
		This option allows the platform to enable experimental extensions,
		LLVM supports (to various degrees) a number of experimental extensions.
		All experimental extensions have experimental- as a prefix. There is
		explicitly no compatibility promised between versions of the toolchain,
		and regular users are strongly advised not to make use of experimental
		extensions before they reach ratification.

config ARCH_RV_ISA_VENDOR_EXTENSIONS
	string "Vendor Custom RISC-V Instruction Set Architecture Extensions"
	default ""
	---help---
		This option allows the platform to enable some vendor-customized ISA extensions,
		E.g OpenHW, SiFive, T-Head.

		SiFive Intelligence Extensions:
		    SiFive Vector Coprocessor Interface(VCIX): xsfvcp
		    SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf
		    SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq
		    SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq
		Command Line:
		    xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1

config ARCH_RV_MMIO_BITS
	int
	# special cases
	default 32 if ARCH_CHIP_K230
	# general fallbacks
	default 32 if ARCH_RV32
	default 64 if ARCH_RV64

config ARCH_RV_HARTID_BASE
	int "Base hartid of this cluster"
	default 0
	---help---
		Some RV chips have multiple cluster of harts with
		globally numbered mhartids, like qemu-rv, mpfs and
		jh7110 etc.  Clusters with SMP ability can be managed
		by NuttX. As NuttX expects cluster-local hart ids,
		we can shift mhartid by this value to derive such
		local ids. The SMP_NCPUS still defines number of
		harts in the cluster. Note that we assume that global
		ids for each cluster are continuous. Note that there
		are chips like k230 which don't have global mhartid.

config ARCH_FAMILY
	string
	default "rv32" if ARCH_RV32
	default "rv64" if ARCH_RV64

config ARCH_CHIP
	string
	default "fe310"                 if ARCH_CHIP_FE310
	default "k210"                  if ARCH_CHIP_K210
	default "litex"                 if ARCH_CHIP_LITEX
	default "bl602"                 if ARCH_CHIP_BL602
	default "esp32c3-legacy"        if ARCH_CHIP_ESP32C3
	default "esp32c3"               if ARCH_CHIP_ESP32C3_GENERIC
	default "esp32c6"               if ARCH_CHIP_ESP32C6
	default "esp32h2"               if ARCH_CHIP_ESP32H2
	default "c906"                  if ARCH_CHIP_C906
	default "mpfs"                  if ARCH_CHIP_MPFS
	default "rv32m1"                if ARCH_CHIP_RV32M1
	default "qemu-rv"               if ARCH_CHIP_QEMU_RV
	default "hpm6000"               if ARCH_CHIP_HPM6000
	default "hpm6750"               if ARCH_CHIP_HPM6750
	default "jh7110"                if ARCH_CHIP_JH7110
	default "bl808"                 if ARCH_CHIP_BL808
	default "k230"                  if ARCH_CHIP_K230
	default "sg2000"                if ARCH_CHIP_SG2000

config ARCH_RISCV_INTXCPT_EXTENSIONS
	bool "RISC-V Integer Context Extensions"
	default n
	---help---
		RISC-V could be customized with extensions. Some Integer Context
		Registers have to be saved and restored when Contexts switch.

if ARCH_RISCV_INTXCPT_EXTENSIONS

config ARCH_RISCV_INTXCPT_EXTREGS
	int "Number of Extral RISC-V Integer Context Registers"
	default 0

endif

config ARCH_MMU_TYPE_SV39
	bool
	default n
	select ARCH_HAVE_MMU

config ARCH_MMU_TYPE_SV32
	bool
	default n
	select ARCH_HAVE_MMU

config ARCH_MMU_EXT_THEAD
	bool "Enable T-Head MMU extension support"
	default n
	depends on ARCH_HAVE_MMU
	---help---
		Enable support for T-Head MMU extension.

config ARCH_HAVE_S_MODE
	bool
	default n

config ARCH_HAVE_MISALIGN_EXCEPTION
	bool
	default n
	---help---
		The chip will raise a exception while misaligned memory access.

config RISCV_MISALIGNED_HANDLER
	bool "Software misaligned memory access handler"
	depends on ARCH_HAVE_MISALIGN_EXCEPTION
	default y

config RISCV_PERCPU_SCRATCH
	bool "Enable Scratch-based Per-CPU storage"
	default y if LIB_SYSCALL
	---help---
		In some special chipsets, multiple CPUs may be bundled in one hardware
		thread cluster, which results in hartid and cpuindex not being exactly
		the same.
		This option will enable Scratch-based Per-CPU storage to distinguish
		the real cpu index.

# Option to run NuttX in supervisor mode. This is obviously not usable in
# flat mode, is questionable in protected mode, but is mandatory in kernel
# mode.
#
# Kernel mode requires this as M-mode uses flat addressing and the kernel
# memory must be mapped in order to share memory between the kernel and
# different user tasks which reside in virtual memory.
#
# Note that S-mode requires a companion software (SBI)
#

config ARCH_USE_S_MODE
	bool "Run NuttX in S-mode"
	default n
	depends on ARCH_HAVE_S_MODE
	select RISCV_PERCPU_SCRATCH
	---help---
		Most of the RISC-V implementations run in M-mode (flat addressing)
		and/or U-mode (in case of separate kernel-/userspaces). This provides
		an option to run the kernel in S-mode, if the target supports it.

config ARCH_RV_EXT_SSTC
	bool "Enable RISC-V SSTC extension support"
	default n
	depends on ARCH_USE_S_MODE

config ARCH_RV_HAVE_APLIC
	bool "Enable RISC-V Advanced Platform-Level Interrupt Controller support"
	default n
	---help---
		Instead of PLIC, RISC-V also defines Advanced Platform-Level Interrupt
		Controller (APLIC) to provide flexible interrupt control. This device
		is not backward compatible with PLIC.

config ARCH_RV_EXT_AIA
	bool "Enable RISC-V SxAIA support"
	default n
	---help---
		Advanced Interrupt Architecture defines necessary features that
		impact the ISA at a hart. This should not be selected if the
		target does not support SxAIA for the operating mode of NuttX.

if ARCH_RV_EXT_AIA

config ARCH_RV_HAVE_IMSIC
	bool "Enable RISC-V AIA Incoming Message Controller support"
	default n

endif # ARCH_RV_EXT_AIA

choice
	prompt "Toolchain Selection"
	default RISCV_TOOLCHAIN_GNU_RV64

config RISCV_TOOLCHAIN_GNU_RV64
	bool "Generic GNU RV64 toolchain"
	select ARCH_TOOLCHAIN_GNU
	---help---
		This option should work for any modern GNU toolchain (GCC 5.2 or newer)
		configured for riscv64-unknown-elf.

config RISCV_TOOLCHAIN_GNU_RV32
	bool "Generic GNU RV32 toolchain"
	select ARCH_TOOLCHAIN_GNU
	---help---
		This option should work for any modern GNU toolchain (GCC 5.2 or newer)
		configured for riscv32-unknown-elf.

config RISCV_TOOLCHAIN_CLANG
	bool "LLVM Clang toolchain"
	select ARCH_TOOLCHAIN_CLANG

config RISCV_TOOLCHAIN_GNU_RV64ILP32
	bool "Generic GNU RV64ILP32 toolchain"
	select ARCH_TOOLCHAIN_GNU
	select ARCH_RV64ILP32
	---help---
		This option work with Ruyisdk toolchain (GCC 13 or newer)
		configured for riscv64-unknown-elf.

endchoice # Toolchain Selection

config RISCV_SEMIHOSTING_HOSTFS
	bool "Semihosting HostFS"
	depends on FS_HOSTFS
	---help---
		Mount HostFS through semihosting.

		This doesn't support some directory operations like readdir because
		of the limitations of semihosting mechanism.

if RISCV_SEMIHOSTING_HOSTFS

config RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
	bool "Cache coherence in semihosting hostfs"
	depends on ARCH_DCACHE
	---help---
		Flush & Invalidte cache before & after bkpt instruction.

endif # RISCV_SEMIHOSTING_HOSTFS

if ARCH_CHIP_LITEX

choice
	prompt "LITEX Core Selection"
	default LITEX_CORE_VEXRISCV

config LITEX_CORE_VEXRISCV
	bool "vexriscv core"

config LITEX_CORE_VEXRISCV_SMP
	bool "vexriscv_smp core"
	select ARCH_HAVE_MPU
	select ARCH_RV_ISA_C
	select ARCH_MMU_TYPE_SV32
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	select ARCH_HAVE_S_MODE
	select ARCH_HAVE_ELF_EXECUTABLE
	select ARCH_HAVE_PERF_EVENTS

endchoice # LITEX Core Selection

endif # ARCH_CHIP_LITEX

source "arch/risc-v/src/opensbi/Kconfig"
source "arch/risc-v/src/nuttsbi/Kconfig"

if ARCH_CHIP_FE310
source "arch/risc-v/src/fe310/Kconfig"
endif
if ARCH_CHIP_K210
source "arch/risc-v/src/k210/Kconfig"
endif
if ARCH_CHIP_LITEX
source "arch/risc-v/src/litex/Kconfig"
endif
if ARCH_CHIP_BL602
source "arch/risc-v/src/bl602/Kconfig"
endif
if ARCH_CHIP_ESP32C3
source "arch/risc-v/src/esp32c3-legacy/Kconfig"
endif
if ARCH_CHIP_ESP32C3_GENERIC
source "arch/risc-v/src/esp32c3/Kconfig"
endif
if ARCH_CHIP_ESP32C6
source "arch/risc-v/src/esp32c6/Kconfig"
endif
if ARCH_CHIP_ESP32H2
source "arch/risc-v/src/esp32h2/Kconfig"
endif
if ARCH_CHIP_C906
source "arch/risc-v/src/c906/Kconfig"
endif
if ARCH_CHIP_MPFS
source "arch/risc-v/src/mpfs/Kconfig"
endif
if ARCH_CHIP_RV32M1
source "arch/risc-v/src/rv32m1/Kconfig"
endif
if ARCH_CHIP_QEMU_RV
source "arch/risc-v/src/qemu-rv/Kconfig"
endif
if ARCH_CHIP_HPM6000
source "arch/risc-v/src/hpm6000/Kconfig"
endif
if ARCH_CHIP_HPM6750
source "arch/risc-v/src/hpm6750/Kconfig"
endif
if ARCH_CHIP_JH7110
source "arch/risc-v/src/jh7110/Kconfig"
endif
if ARCH_CHIP_BL808
source "arch/risc-v/src/bl808/Kconfig"
endif
if ARCH_CHIP_K230
source "arch/risc-v/src/k230/Kconfig"
endif
if ARCH_CHIP_SG2000
source "arch/risc-v/src/sg2000/Kconfig"
endif
endif # ARCH_RISCV