2019-08-15 18:19:17 +02:00
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/****************************************************************************
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* boards/arm/sam34/sam3u-ek/include/board.h
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2009-12-31 23:30:26 +01:00
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*
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2013-06-02 18:33:57 +02:00
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* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
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2011-10-08 00:37:24 +02:00
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* Author: Gregory Nutt <gnutt@nuttx.org>
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2009-12-31 23:30:26 +01:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2009-12-31 23:30:26 +01:00
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2019-08-15 18:19:17 +02:00
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#ifndef __BOARDS_ARM_SAM34_SAM3U_EK_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAM34_SAM3U_EK_INCLUDE_BOARD_H
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2009-12-31 23:30:26 +01:00
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2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2009-12-31 23:30:26 +01:00
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* Included Files
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2009-12-31 23:30:26 +01:00
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#include <nuttx/config.h>
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2010-01-23 04:05:05 +01:00
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2009-12-31 23:30:26 +01:00
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#ifndef __ASSEMBLY__
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2010-01-23 04:05:05 +01:00
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# include <stdint.h>
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2014-03-23 22:48:10 +01:00
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# ifdef CONFIG_SAM34_GPIO_IRQ
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2010-01-23 04:05:05 +01:00
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# include <arch/irq.h>
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# endif
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2009-12-31 23:30:26 +01:00
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#endif
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2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2015-04-08 17:15:17 +02:00
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* Pre-processor Definitions
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2009-12-31 23:30:26 +01:00
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2019-08-15 18:19:17 +02:00
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/* Clocking *****************************************************************/
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/* After power-on reset, the sam3u device is running on a 4MHz internal RC.
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* These definitions will configure clocking
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2013-06-17 16:41:52 +02:00
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*
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* MAINOSC: Frequency = 12MHz (crysta)
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* PLLA: PLL Divider = 1, Multiplier = 16 to generate PLLACK = 192MHz
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* Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 96MHz
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* CPU clock: 96MHz
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2010-01-17 18:55:13 +01:00
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*/
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2013-06-17 16:41:52 +02:00
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/* Main oscillator register settings.
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*
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* The start up time should be should be:
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* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
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*/
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2010-01-17 18:55:13 +01:00
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2013-06-17 16:41:52 +02:00
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#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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2010-01-17 18:55:13 +01:00
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2013-06-17 16:41:52 +02:00
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/* PLLA configuration.
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*
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* Divider = 1
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* Multipler = 16
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*/
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2010-01-17 18:55:13 +01:00
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2013-06-17 16:41:52 +02:00
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#define BOARD_CKGR_PLLAR_MUL (15 << PMC_CKGR_PLLAR_MUL_SHIFT)
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2013-06-10 19:57:37 +02:00
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#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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2010-01-17 18:55:13 +01:00
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2013-06-17 16:41:52 +02:00
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/* PMC master clock register settings.
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*
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* Source = PLLA
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* Divider = 2
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*/
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2010-01-17 18:55:13 +01:00
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
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/* USB UTMI PLL start-up time */
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2013-06-12 01:33:43 +02:00
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#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
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2010-01-17 18:55:13 +01:00
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/* Resulting frequencies */
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2013-06-17 16:41:52 +02:00
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_PLLA_FREQUENCY (192000000) /* PLLACK: 16 * 12Mhz / 1 */
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#define BOARD_MCK_FREQUENCY (96000000) /* MCK: PLLACK / 2 */
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#define BOARD_CPU_FREQUENCY (96000000) /* CPU: MCK */
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2009-12-31 23:30:26 +01:00
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2010-04-07 05:00:34 +02:00
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV+1)).
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*
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* MCI_SPEED = MCK / (2*(CLKDIV+1))
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* CLKDIV = MCI / MCI_SPEED / 2 - 1
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2013-06-17 16:41:52 +02:00
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*
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* Where CLKDIV has a range of 0-255.
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2010-04-07 05:00:34 +02:00
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*/
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2013-06-17 16:41:52 +02:00
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/* MCK = 96MHz, CLKDIV = 119, MCI_SPEED = 96MHz / 2 * (119+1) = 400 KHz */
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2013-06-02 18:33:57 +02:00
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2013-06-17 16:41:52 +02:00
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#define HSMCI_INIT_CLKDIV (119 << HSMCI_MR_CLKDIV_SHIFT)
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2010-04-07 05:00:34 +02:00
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2013-06-17 16:41:52 +02:00
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/* MCK = 96MHz, CLKDIV = 3, MCI_SPEED = 96MHz / 2 * (3+1) = 12 MHz */
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2010-04-07 05:00:34 +02:00
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2013-06-12 16:18:42 +02:00
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#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT)
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2010-04-07 05:00:34 +02:00
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2013-06-17 16:41:52 +02:00
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/* MCK = 96MHz, CLKDIV = 1, MCI_SPEED = 96MHz / 2 * (1+1) = 24 MHz */
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2010-04-07 05:00:34 +02:00
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2013-06-27 22:24:27 +02:00
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#define HSMCI_SDXFR_CLKDIV (1 << HSMCI_MR_CLKDIV_SHIFT)
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2013-06-12 16:18:42 +02:00
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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2013-06-17 16:41:52 +02:00
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/* FLASH wait states
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*
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* FWS Max frequency
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* 1.62V 1.8V
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* --- ----- ------
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* 0 24MHz 27MHz
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* 1 40MHz 47MHz
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* 2 72MHz 84MHz
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* 3 84MHz 96MHz
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*/
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2013-06-12 16:18:42 +02:00
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2013-06-17 16:41:52 +02:00
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#define BOARD_FWS 3
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2010-04-07 05:00:34 +02:00
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2019-08-15 18:19:17 +02:00
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/* LED definitions **********************************************************/
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2009-12-31 23:30:26 +01:00
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2010-01-22 04:08:29 +01:00
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#define LED_STARTED 0 /* LED0=OFF LED1=OFF LED2=OFF */
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#define LED_HEAPALLOCATE 1 /* LED0=OFF LED1=OFF LED2=ON */
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#define LED_IRQSENABLED 2 /* LED0=OFF LED1=ON LED2=OFF */
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#define LED_STACKCREATED 3 /* LED0=OFF LED1=ON LED2=ON */
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2010-01-22 04:45:25 +01:00
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#define LED_INIRQ 4 /* LED0=XXX LED1=TOG LED2=XXX */
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#define LED_SIGNAL 5 /* LED0=XXX LED1=XXX LED2=TOG */
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2010-01-22 04:08:29 +01:00
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#define LED_ASSERTION 6 /* LED0=TOG LED1=XXX LED2=XXX */
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2010-01-23 04:05:05 +01:00
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#define LED_PANIC 7 /* LED0=TOG LED1=XXX LED2=XXX */
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2019-08-15 18:19:17 +02:00
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/* Button definitions *******************************************************/
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2010-01-23 04:05:05 +01:00
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#define BUTTON1 1 /* Bit 0: Button 1 */
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#define BUTTON2 2 /* Bit 1: Button 2 */
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2010-01-19 03:00:14 +01:00
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2019-08-15 18:19:17 +02:00
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#endif /* __BOARDS_ARM_SAM34_SAM3U_EK_INCLUDE_BOARD_H */
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