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0e67dc8637
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33 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
0e67dc8637 xtensa/esp32s3: Add support for GPIO read/write operations 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 07:23:51 +09:00
Petro Karashchenko
68902d8732 pid_t: unify usage of special task IDs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-22 21:22:32 +08:00
Gustavo Henrique Nihei
9ae826e925 xtensa/esp32s3: Fix output handling for pins numbered from 32 to 48 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
f21a9f9578 xtensa/esp32s3: Enable UART pins to use IOMUX and bypass GPIO matrix 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
77944ceb42 xtensa/esp32s3: Clean up and improve GPIO driver interface 
Also fix an inconsistenct regarding the ESP32S3_NGPIOS macro. Although
correctly defining the number of available GPIOs in ESP32-S3, it was
erroneously being used for verifying the pin range.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
43b7d9b0da xtensa/esp32s3: Sync GPIO sigmap with IDF version 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Abdelatif Guettouche
5085f854d0 esp32(s3)_start.c: In SMP mode, don't disable APP CPU at startup. It starts in a 
disabled state and if OpenOCD is used this will clear OpenOCD configuration.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-17 14:33:32 -03:00
Abdelatif Guettouche
b98676f8be esp32(s3)_cpustart.c: Don't reset app CPU if it was already configured by 
OpenOCD.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-17 14:33:32 -03:00
Gustavo Henrique Nihei
39e9a17e60 xtensa/esp32s3: Apply style fixes throughout serial driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Gustavo Henrique Nihei
0dc2930403 xtensa/esp32s3: Remove code for not yet supported USB-Serial Driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Gustavo Henrique Nihei
57273ad994 xtensa/esp32s3: Fix IRQ setup hardcoded to CPU 0 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-16 19:06:39 -03:00
Petro Karashchenko
b04447d066 timer_lowerhalf: minor improvements 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-15 10:30:48 +08:00
Gustavo Henrique Nihei
7ede285cfe xtensa/esp32s3: Add support for RT-Timer based on Systimer peripheral 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 15:27:30 +02:00
Gustavo Henrique Nihei
86b18bd6e9 xtensa/esp32s3: Move code documentation to the correct place 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 11:53:14 +08:00
Gustavo Henrique Nihei
a4db4031c9 xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-12 11:53:14 +08:00
Xiang Xiao
39fb09738d arch: Move [arm|xtensa]_intstack_[alloc|top] to common header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-11 23:08:07 +02:00
Gustavo Henrique Nihei
c8796c1bc2 xtensa/esp32s3: Move SPI RAM configuration out of Peripheral menu 
Menu for configuration of SPI RAM was wrongly placed inside the menu
for peripheral selection.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-11 11:05:24 +08:00
Alan C. Assis
dc1b6776b9 xtensa/esp32s3: Add SPI RAM/PSRAM Support 2022-03-09 19:22:56 +02:00
Gustavo Henrique Nihei
4a29fa903b xtensa/esp32s3: Enable SMP support 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-09 10:42:50 +08:00
Abdelatif Guettouche
c820085a23 arch/xtensa/esp32s3: Add encrypted support for SPI FLASH. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-03 19:57:59 +08:00
Abdelatif Guettouche
9d5b13cd0e xtensa/esp32s3: Add SPI-Flash support. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-03 19:57:59 +08:00
Gustavo Henrique Nihei
16030f713e xtensa/esp32s3: Add support for Free-running Timer 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-03 10:58:53 +08:00
Gustavo Henrique Nihei
3b7a6ae311 xtensa/esp32s3: Add support for Tickless kernel using Systimer 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-02 18:08:44 +01:00
zhuyanlin
fbc1da98b7 xtensa: use swint to swith context 
Reason for use sw-interrupt as syscall interrupt:
The xtensa `syscall` instruction can cause SYSCALL interrupt.
But SYSCALL interrupt is same interrupt level with level-one
interrupt.
Nuttx swint can enter `enter_critical_section` and gerenate
interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-25 20:43:03 +08:00
Gustavo Henrique Nihei
ea1b49119a xtensa/esp32s3: Apply minor fixes to documentation and code style 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 10:51:25 +08:00
Gustavo Henrique Nihei
add99fead3 xtensa/esp32s3: Add support for Oneshot timer 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 10:51:25 +08:00
Gustavo Henrique Nihei
b49ee3d4ed xtensa/esp32s3: Add support for Main System Watchdog Timers 
Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 02:13:00 +08:00
Gustavo Henrique Nihei
a5024a707d xtensa/esp32s3: Use the running CPU ID for enabling internal interrupts 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-24 17:43:39 +01:00
Gustavo Henrique Nihei
83f3ba6d22 xtensa/esp32s3: Add support for Timer Groups 0 and 1 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-02-25 00:13:34 +08:00
zhuyanlin
fc9791c269 xtensa:esp32s3: setup software interrupt as swi interrupt. 
Enable and setup software interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-24 00:06:43 +01:00
Abdelatif Guettouche
ab18b7b3d3 esp32xx_irq.c: Fix CPU interrupt documentation to remove the MAC 
interrupt from the internal interrupt table.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-02-18 13:40:21 +08:00
Xiang Xiao
4c167b0729 Correct the code alignment 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-01 21:22:21 -03:00
Gustavo Henrique Nihei
b0d24f53c4 xtensa: Add initial support for ESP32-S3 
Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-27 13:46:50 -03:00