Commit Graph

904 Commits

Author SHA1 Message Date
SPRESENSE
de8829f8cd arch: cxd56xx: Fix SCU sensor data format
Add offset setting for sensor data to be written to SCU math function.
Fix comments in function descriptions.
2024-08-27 12:28:50 +02:00
Petro Karashchenko
d499ac9d58 nuttx: fix multiple 'FAR', 'CODE' and style issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-08-25 19:22:15 +08:00
chao an
a0afd38f24 arm/spinlock: up_testset() sould not depends on SMP
up_testset() sould not depends on SMP

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-23 20:20:06 +08:00
guoshichao
24ce8dfbf2 armv7-a/irq: add up_irq_disable method implementation
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
(cherry picked from commit 7059b05e501d67c342f1753e8eb96e723b99d6b8)
2024-08-21 02:53:04 +08:00
guoshichao
0aa7e39eef nuttx/arch/irq: add up_irq_disable method implementation
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-21 02:53:04 +08:00
hujun5
4cb419866f arch: inline up_testset in arm arm64 riscv xtensa
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-08-21 01:45:10 +08:00
guoshichao
07c370817c armv7a/irq: enable fiq in tee, enable irq in ap
According to the current design on the armv7-a platform,
only fiq is processed in TEE, while irq and fiq are processed
in REE.
If we enable the irq function in TEE, when we process
some signal-related scenarios in TEE,
such as the ostest sighand testcase, this testcase will
call up_irq_enable() to enable irq interrupt in the
arm_sigdeliver() function. After the signal processing
logic is executed, irq will be disabled again.
During the interval of enabling irq, some external device
irq interrupts will be enabled, but these external device
irqs do not have corresponding handlers registered in TEE,
so an "unexpected irq isr exception" will be triggered.
Therefore, a better implementation is to keep the original
implementation of the up_irq_enable() function, that is,
to enable only fiq in TEE and to enable irq and fiq in REE.
Then  for vendor-specific requirements, such as the need to
briefly enable irq during the TEE initialization process
and then disable irq before starting APz in TEE, we directly
provide a separate implementation of enabling irq in the
vendor, without modifying the implementation of the public
up_enable_irq() function.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-21 01:36:32 +08:00
yanghuatao
b3627bb8c6 toolchain/ghs: Fix zero used for undefined preprocessing identifier "NR_IRQS" warnings
CC:  unistd/lib_setregid.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 53: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #  if NR_IRQS <= 256
        ^
"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 82: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #if NR_IRQS <= 256
CC:  mount/fs_umount2.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 72: warning #193-D:
          zero used for undefined preprocessing identifier "NR_IRQS"
  #if NR_IRQS <= 256

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-19 10:37:54 +08:00
guoshichao
0cf0bece2e arch/strarg: provide the stdarg implementation for greenhills compiler
the greenhills compiler provide its own implementation of va_start,
va_end, va_arg, va_copy. so if we are build vela with greenhills
compiler, we should using the stdarg implementation provided by
greenhills, not our own

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
2024-08-19 10:37:54 +08:00
chenxiaoyi
7ce5241f0e types.h: fix windows build error
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(605,39): error C2371: 'wint_t': redefinition; different basic types
Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt.h(606,39): error C2371: 'wctype_t': redefinition; different basic types

Co-authored-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Co-authored-by: xuxin19 <xuxin19@xiaomi.com>
2024-08-14 22:36:57 +08:00
yanghuatao
fecc5091af toolchain/ghs: Fix SP_DSB warnings
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
          argument to macro is empty
    SP_DMB();
           ^

"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
          argument to macro is empty
        SP_DSB();
               ^

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:28:12 -03:00
fangxinyong
6da525704d toolchain/ghs: fix the inline assembly code register alloc compile error
The following are the compile error that reported
by GreenHills compiler:

"/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 156 (col. 17): error #2036-D:
          cannot allocate "reg0" to specified caller-saved register

 "/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 157 (col. 17): error #2036-D:
          cannot allocate "reg1" to specified caller-saved register

Then we fix this greenhills compilation error by explicitly specifying
the registers in the clobber list in the inline assembly code.
This fix is successful in compiling on the
nuttx/boards/arm/mps/mps2-an500/configs/nsh platform and passes
the ostest test.
However, if we keep the implementation the same for both the default
and Greenhills compilers, the default compiler will report the
following two issues:
1. the "sys_call6" function will report compile error when
compiling on "./vendor/qemu/boards/smartspeaker/configs/smartspeaker-knsh"
platform, the detailed error info:

CC:  proxies/PROXY_mq_getattr.c In file included from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/sys/syscall.h:35,
                 from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/syscall.h:30,
                 from proxies/PROXY_mmap.c:5:
In function 'sys_call6',
    inlined from 'mmap' at proxies/PROXY_mmap.c:9:22:
/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/syscall.h:297:3: error: 'asm' operand has impossible constraints
  297 |   __asm__ __volatile__
      |   ^~~~~~~

2. when running on qemu-armv7-a platform, the modification to
"smh_call()" function will make the system fail to boot up, so
we need to keep the default compiler implementation and greenhills
compiler implementation separate

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
(cherry picked from commit cb48b749b1c9cad8cfb96bff7c5e9b6ebf20fc8a)
2024-08-11 14:28:12 -03:00
yanghuatao
3e171489bd toolchain/ghs: Fix green hills toolchain build Vela link error
[elxr] (error #412) unresolved symbols:
 __builtin_frame_address     from libarch.a(arm_checkstack.o)

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2024-08-11 14:27:02 -03:00
chao an
b191153cdc arch/armv8-r: fix typos in config
replace ARMV7R to ARMV8R

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-10 18:41:13 -03:00
Takuya Miyashita
146975d069 arch: cxd32xx: Add cxd32xx SoC support
Supported drivers
 - Serial(PL011), Timer, NVIC
2024-06-04 22:21:56 +08:00
jfbblue0922
72c1f779d1 add stm32h755II chip 2024-05-17 10:16:39 -03:00
anjiahao
1ea10ddacc mps3:Support NuttX running on qemu cortex-m55
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-04-26 18:42:35 -03:00
zhangyuan21
9c0d2e1a3c armv7-a/gicv2: move IRQ to group1 and group0 as the FIQ
Purpose: make the the os crash when busyloop with interrupt disable

Follow the arm gicv2 spec, if we want to use the IRQ and FIQ
simultaneously when not using the processor Security Externsions.
We should:
1. IRQ to Group 1 and FIQ to Group 0;
2. Set CICC_CTLR.FIQEn to 1;

Then in NuttX:
1. implement the arm_decodefiq and directly crash in it;
2. provide interface to change the IRQ to FIQ, e.g. change the
   watchdog IRQ to FIQ, so the watchdog can trigger even with the
   interrupt disabled (up_irq_save() called);

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-19 18:24:42 +09:00
Yanfeng Liu
a66c7c3ee1 comments/docs: fix typos in comments
This fix some typos in comments.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-06 13:31:50 +08:00
Tiago Medicci Serrano
ae9ef972c0 paging: Rename existing CONFIG_PAGING to CONFIG_LEGACY_PAGING
Current `CONFIG_PAGING` refers to an experimental implementation
to enable embedded MCUs with some limited RAM space to execute
large programs from some non-random access media.

On-demand paging should be implemented for the kernel mode with
address environment implementation enabled.
2024-03-05 09:45:49 +08:00
SPRESENSE
a303ec8653 arch: cxd56xx: Add new feature to use GNSS RAM
As long as the GNSS feature is not used, GNSS RAM can be used as general memory.
This memory is 640KByte total, which is lower performance than the application RAM.
It is possible to locate text, data and bss into GNSS RAM and to use as heap area.
2024-02-05 05:53:51 -08:00
Rodrigo Sim
21b02f176f stm32f401rc-rs485: Add rs-485 support 2024-01-07 17:15:59 -08:00
simbit18
c494ce4a96 Update kconfig2html.c
Fix nuttx coding style
2023-12-14 20:02:52 -08:00
simbit18
9d50d180b1 Fix nuttx coding style
Remove spaces
Remove extra */
2023-12-13 17:29:08 +01:00
Xiang Xiao
ca5a9c711a Remove @ and % tag from all comments
and format the multiple line comments

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-11 17:00:10 -03:00
anjiahao
94d449e722 arch:Mark key functions to prohibit instrumentation to prevent recursive calls
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
Peter van der Perk
9906163beb Base IMXRT1170 port
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>

Co-authored-by: David Sidrane <david.sidrane@nscdg.com>

Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>

imxrt:Kconfig fix formatting

imxrt:usbphy move IMXRT_USBPHY{1|[2]}_BASE to memory map

imxrt:lpspi Fix build breakage from adding 1170

imxrt:Finish 1170 iomux and clockconfig versioning

imxrt:Remove duplicate imxrt_clock{off|all}_lpi2c4

imxrt:pmu remove duplicate dcd non 117x header

imxrt:lpspi Fix unused var warnings

imxrt:lpi2c Fix unused var warnings

imxrt:lowputs Fix unused var warnings

imxrt:imxrt117x_dmamux fix duplicate entries

imxtr:serial Use IOMUX_PULL_{UP|DOWN} and map IOMUX V1 to them

imxrt:MPU Support the 1170

imxrt:dmamux Alias IMXRT_DMAMUX0_BASE as IMXRT_DMAMUX_BASE

imx1170:ccm Alias CCM_CCGR_DMA & CCM_CCGR_SNVS_LP for compatiblity

Author: Peter van der Perk <peter.vanderperk@nxp.com>

IMXRT7 Add LPUART 9/10/11/12 support

Author: David Sidrane <david.sidrane@nscdg.com>

imxrt:1170pinmux Add QTIMER pins

imxrt:1170pinmux Add GPT pins

imxrt:1170pinmux Add FLEXPWM pins

imxrt1170:pinmap Add GPIO_ENET_1G pinning

imxrt:enet Support ENET_1G

imxrt:periphclks rt1170 does not have canX_serial clock

imxrt:flexcan:Layer imxrt_ioctl

imxrt117x:memorymap added CAN3

imxrt:ADC support ver1 and ver2 for imxrt117x

imxrt:imxrt117x_ccm Align timer naming with other imxrt QTIMERn->TIMERn

imxrt:imxrt117x_ccm align CCM names with rt106x

imxrt:XBAR support larger number of selects needed on imxrt1170

Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>

FlexSPI AHB Region support, PIT rename for compatiblity

imxrt:USB Analog add VBUS_VALID_3V

FlexSPI expand prefetch registers for IMXRT117X

imxrt:Support Initialization of FlexRam without Running from OCRAM

imxrt: ocotp add UNIQUE_ID register definition

imxrt: enet use ocotp unique_id

imxrt: enet fixes for imxrt117x

imxrt: ethernet pinmux sion enable

imxrt:imxrt_periphclk_configure add memory sync

   Flush the pipeline to prevent bus faults, by insuring a
   peripheral is clocked before being accessed on return from
   this function.

imxrt:Restructure gpioN to padmux mapping

imxrt:Add imxrt1170 daisy

imxrt: correct power modes for imxrt117x fixing hang on WFI

imxrt: imxrt117x TCM MPU config

imxrt: FlexRAM clocking DIV0 setup

imxrt: 117x periphclocks wait for status bit

imxrt: iomucx set pad settings correctly and allow reconfiguration

imxrt: enet align buffers 64-byte for optimal performance

Add DSC barriers for write-through cache support

imxrt: imxrt1170 use FlexCAN FD/ECC features

imxrt:iomuxc_ver2 (117x) SD_B1 and DISP_B1 use PULL feild not PUE/PUS

imxrt:Fix 1170 SNVS addressing

imxrt: enet set mii clock after ifdown so that phy keep working

nxstyle fixes

imxrt: preprocessor and include fixes

Fix configs

imxrt1170-evk clean defconfig
2023-12-07 03:48:19 -08:00
Janne Rosberg
03064b9701 sama5: add support for QSPI 2023-11-08 21:58:02 +01:00
SPRESENSE
ed5785ad06 arch: cxd56xx: Update gnss header files
- Add some ioctl commands to get version, sleep, wakeup and reset.
- Add new data structures for CXD5610 GNSS Add-on board.
2023-10-31 09:18:18 +01:00
GD32-MCU
6e94f7432f add gd32f470i board support 2023-10-21 11:45:03 -03:00
Simon Filgis
882afc885e channel gain switching in aefc by ioctl
Update arch/arm/include/samv7/sam_afec.h

remove "offset may be uninitialized" warning

Update arch/arm/include/samv7/sam_afec.h

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/include/samv7/sam_afec.h

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/src/samv7/sam_afec.c

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/src/samv7/sam_afec.c

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/include/samv7/sam_afec.h

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/include/samv7/sam_afec.h

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

remove blank line
2023-10-16 21:55:40 +08:00
simbit18
34bb0b6544 Fix nuttx coding style
Remove TABs
Remove spaces
Fix indentation
2023-09-21 10:03:13 -04:00
xiao
1487aa267e add Artery at32
check nxstyle

check nxstyle
2023-09-20 02:07:55 +08:00
Xiang Xiao
8dbe86084e Remove FAR from source code under 32bit arch and board
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-16 19:12:13 +03:00
wangming9
72cf51faf3 arm/psci: Fixed arm psci related compilation errors
Summary
include/arch/syscall.h: Assembler messages:
include/arch/syscall.h:133: Error: bad instruction `struct arm_smccc_res'
include/arch/syscall.h:134: Error: junk at end of line, first unrecognized character is `{'
include/arch/syscall.h:135: Error: bad instruction `unsigned long a0'
include/arch/syscall.h:136: Error: bad instruction `unsigned long a1'
include/arch/syscall.h:137: Error: bad instruction `unsigned long a2'
include/arch/syscall.h:138: Error: bad instruction `unsigned long a3'
include/arch/syscall.h:139: Error: bad instruction `unsigned long a4'
include/arch/syscall.h:140: Error: bad instruction `unsigned long a5'
include/arch/syscall.h:141: Error: bad instruction `unsigned long a6'
include/arch/syscall.h:142: Error: bad instruction `unsigned long a7'
include/arch/syscall.h:143: Error: junk at end of line, first unrecognized character is `}'
include/arch/syscall.h:145: Error: bad instruction `typedef struct arm_smccc_res

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-09-13 21:06:51 +08:00
Shanmin Zhang
b9fb9bea1d arm: support reboot / poweroff for qemu virt arm
Signed-off-by: Shanmin Zhang <zhangshanmin@xiaomi.com>
2023-09-12 21:57:13 +08:00
wangming9
c8a4bdf21a arch/arm: GoldFish Platform support
Summary:
    Adding virtual evaluate platform GoldFish. Which is based on
    Android Goldfish Emulator, it's a ARM virt board but Android
    enhance it with more featue.
    The patch set goldfish as a arm chip.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-09-10 23:10:06 +08:00
Philippe Leduc
87cec56154 Handle GPIO IRQs
Add board buttons
2023-09-06 12:30:35 +08:00
Michal Lenc
03e5c0217b samv7: allow usage of QSPI in SPI mode for all MCUs
Current implementation of QSPI in SPI mode was available only for MCUs
that do not have standard SPI at all. MCUs with both QSPI and SPI can
however also use QSPI in SPI mode and thus have one more SPI bus. This
commit adds required defines and config options to support QSPI in SPI
mode for all SAMv7 MCUs.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-08-28 17:39:51 +03:00
raiden00pl
a6c25f657d arch/stm32h7: add CM4 core support 2023-08-26 03:35:32 +08:00
SPRESENSE
f7400a857d drivers/audio/cxd56: Move cxd56 sources into arch/cxd56xx
CXD56 audio functions are inside of the CXD56.
So implementation of it should be under arch directory.
2023-08-26 01:20:32 +08:00
Philippe Leduc
e084c52e12 Add i.MX8MP Cortex-M7 port for NuttX 2023-08-24 20:10:48 +08:00
wangming9
e953715e6d arch/arm: add qemu support for ARM32
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-15 23:56:41 +08:00
Petro Karashchenko
d113722eb2 style: fix indentation issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-08-08 11:58:29 -03:00
wangming9
f8aaed780a arch/armv8-m: Add CONTROL register to xcptcontext.
To simplify the interrupt handling in protected mode.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
cedc034d9e arch/tlsr82: Port arm_doirq to tc32_doirq.c
Solve the dependency on ARMV6M when compiling tlsr8278adk80d:nsh.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
eba9c61cad arch/armv6-m: Add CONTROL register to xcptcontext.
To simplify the interrupt handling in protected mode.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
a4b6b158ce arch/armv6-m: By default, add REG_EXC_RETURN to xcptcontext.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
4370487fd6 arch/armv7-m: Add CONTROL register to xcptcontext.
To simplify the interrupt handling in protected mode.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
yangyalei
fde8affe71 singal: add stack_t define
stack_t used by sigaltstack, make it compile sucess in sim.

Signed-off-by: yangyalei <yangyalei@xiaomi.com>

ltp: fix compile errors

Signed-off-by: yangyalei <yangyalei@xiaomi.com>
2023-07-31 07:50:10 -07:00