stm32_i2sdev_initialize to stm32_i2sbus_initiliaze, to be consistent
with the way other buses are initialized.
The stm32_i2sdev_initiliaze (similar to stm32_spidev_initialize for
example) is a board specific function that does any necessary
initialization that's board depedent.
utilize the call inside nxtask_exit instead, also move
nxsched_suspend_scheduler to nxtask_exit for symmetry
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I219fc15faf0026e452b0db3906aa40b40ac677f3
This fixes the following 3 issues:
1. Wait for send to complete in exchange
Before shutting down the SPI, we have to wait for send to complete; not only
DMA, since DMA just puts data to the SPI fifo. It is not yet out of SPI.
When doing exchange with both send & receive this is not an issue because when
receive dma has completed, it is certain that also the send is.
This can be accomplished by completing the transfer in SPI TXC interrupt
instead of DMA callback.
2. Fix TXDMAEN and RXDMAEN placement
According to the spec, the RXDMAEN must be enabled before
enabling DMA requests for Tx and Rx in DMA registers, and TXDMAEN
after that.
Cleaner place to do this is in spi_dmarxstart and spi_dmatxstart, where
also the dma requests are enabled. This also handles properly the
simplex modes.
3. Remove bus signal glitches when shutting off SPI block
Use AFCNTR to avoid glitches in SPI lines while turning SPI block
on/off during calls to exchange.
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
arch/z80/src/Makefile: Correct inclusion of non-existent file. This was not a problem before because there was '-' before the include. Problem revealed with '-' removed.
arch/z80/src/ez80/Toolchain.defs: Apparently there are not too many '"' in path definition.
tools/incdir.c: No space between -usrinc: or -sysinc: and the list of paths.
574b25 broke the internal DMA buffers usage that solved
the following problem: The DMA capable interface does
not know the buffers extent. It calulates it from size.
The user may need to transfer less than a cachline bytes,
but STILL have a DMA cabable buffer. The user is therefore
foreced to transfer more data then needed to "trick" the
DMA cabable function. This is a wast of bus bandwith and
may not work will all devices. The internal buffer, solve
this issue.
stm32h7:stm32_spi review changes
Added sugestion from jlaitine to support RX only.
This is a work in progress, and now only serves as
DMA enabled simplex RX-only mode bus controller
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
-Move task_init() and task_activate() prototypes from include/sched.h to include/nuttx/sched.h. These are internal OS functions and should not be exposed to the user.
-Remove references to task_init() and task_activate() from the User Manual.
-Rename task_init() to nxtask_init() since since it is an OS internal function
-Rename task_activate() to nxtask_activate since it is an OS internal function
Add support for the STM32G474 family of microcontrollers and the
B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.
This is a major pull request as it adds support for an entirely
new family of STM32. This support is implemented in
arch/arm/src/stm32 and shares implementation with other STM32
families supported by that code, such as the 'L15xx, 'F10xx,
'F20xx, 'F3xxx, and 'F4xxx.
arch/arm/Kconfig:
arch/arm/include/stm32/chip.h:
arch/arm/include/stm32/irq.h:
arch/arm/src/stm32/Kconfig:
arch/arm/src/stm32/hardware/stm32_adc.h:
arch/arm/src/stm32/hardware/stm32_adc_v2.h:
arch/arm/src/stm32/hardware/stm32_dma.h:
arch/arm/src/stm32/hardware/stm32_dma_v1.h:
arch/arm/src/stm32/hardware/stm32_flash.h:
arch/arm/src/stm32/hardware/stm32_i2c.h:
arch/arm/src/stm32/hardware/stm32_i2c_v2.h:
arch/arm/src/stm32/hardware/stm32_memorymap.h:
arch/arm/src/stm32/hardware/stm32_pinmap.h:
arch/arm/src/stm32/hardware/stm32_tim.h:
arch/arm/src/stm32/stm32_allocateheap.c:
arch/arm/src/stm32/stm32_dma.c:
arch/arm/src/stm32/stm32_dma_v1.c:
arch/arm/src/stm32/stm32_dumpgpio.c:
arch/arm/src/stm32/stm32_gpio.c:
arch/arm/src/stm32/stm32_gpio.h:
arch/arm/src/stm32/stm32_lowputc.c:
arch/arm/src/stm32/stm32_rcc.c:
arch/arm/src/stm32/stm32_rcc.h:
arch/arm/src/stm32/stm32_serial.c:
arch/arm/src/stm32/stm32_syscfg.h:
arch/arm/src/stm32/stm32_uart.h:
* Add architectural support to existing NuttX files. This
makes the STM32G474 family parts accessible to the system.
With big thanks for detailed code review:
David Sidrane (davids5)
Mateusz Szafoni (raiden00)
Abdelatif Guettouche (Ouss4)
Add support for the STM32G474 family of microcontrollers and the
B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.
This is a major pull request as it adds support for an entirely
new family of STM32. This support is implemented in
arch/arm/src/stm32 and shares implementation with other STM32
families supported by that code, such as the 'L15xx, 'F10xx,
'F20xx, 'F3xxx, and 'F4xxx.
arch/arm/include/stm32/stm32g47xxx_irq.h:
arch/arm/src/stm32/hardware/stm32g474cxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474mxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474qxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474rxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g474vxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_gpio.h:
arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h:
arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h:
arch/arm/src/stm32/hardware/stm32g47xxx_rcc.h:
arch/arm/src/stm32/hardware/stm32g47xxx_syscfg.h:
arch/arm/src/stm32/hardware/stm32g47xxx_uart.h:
arch/arm/src/stm32/stm32g47xxx_rcc.c:
* New files required for architectural support. Note that
existing NuttX files are not modified. As such, in this
revision, the system is unaffected by their addition.
With big thanks for detailed code review:
David Sidrane (davids5)
Mateusz Szafoni (raiden00)
Abdelatif Guettouche (Ouss4)
remove the TLS alignment check
Regression by:
--------------------------------------------------------
commit a6da3c2cb6
Author: Ouss4 <abdelatif.guettouche@gmail.com>
Date: Thu May 7 18:50:07 2020 +0100
arch/*/*_checkstack.c: Get aligned address only when
CONFIG_TLS_ALIGNED is enabled.
--------------------------------------------------------
commit c2244a2382
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Thu May 7 09:46:47 2020 -0600
Remove CONFIG_TLS
A first step in implementing the user-space error is
force TLS to be enabled at all times. It is no longer optional
Signed-off-by: chao.an <anchao@xiaomi.com>
For SDMMC1, IDMA cannot access SRAM123 or SRAM4. Refer to ST AN5200 for
details. This patch makes stm32_dmapreflight check the buffer address and
return an error when the buffer is located in a invalid address space.
This does not fix the hardware limitation but at least makes it visible.
This simplifies the sdmmc driver when the IDMA is in use. There is no need to mix
IDMA and interrupt based transfers; instead, when making unaligned data tranfers,
just make IDMA into an internal aligned buffer and then copy the data.
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
It should not be an error to clean cache beyond the dma source buffer
boundaries. It would just prematurely push some unrelated data from
cache to memory.
The only case where it would corrupt memory is that there is a dma
destination buffer overlapping the same cache line with the source
buffer. But this can't happen, because a destination buffer must always
be cache-line aligned when using write-back cache.
This patch enables doing dma tx-only transfer from unaligned source
buffer when using write-back cache.
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
Correct flash write and erase functions, they inherit some
broken code from other platforms. Also fix the confusion between
eraseblock(sector) and page sizes.
Signed-off-by: Jari Nippula <jari.nippula@intel.com>
If the flash option register was locked before modifying it, return
it to the locked state after modify.
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
Remove support for the Codesourcery, Atollic, DevKitArm, Raisonance, and CodeRed toolchains. Not only are these tools old and no longer used but they are all equivalent to standard ARM EABI toolchains. Retaining specific support has no effect (they are still supported, but now just as generic EABI toolchains).
First, configure the dmacfg in spi_dmarxsetup and spi_dmatxsetup. Then,
check for dmacapable, and only after that set up the dma.
This way the dmacapable actually works, and we don't need to initialize
the dmacfg structures twice.
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
When starting dma transfer, the dcache for the TX buffer should be cleaned.
"flush" performs also invalidate, which is unnecessary. The TX buffer
can be unaligned to the cahche line in some(most) cases, whereas RX buffer
can never be.
The cache for the receive buffer can be dirty and valid before call to exchange.
Thus another memory access (hitting the same cache line) may corrupt receive data
while waiting for transfer to complete. So the receive buffer should be
invalidated before the transfer
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
Modify some comments and debug assertions, which inherit from previous versions
and make no sense. Also add a few nerr printouts to make it easier to debug
running out of buffers
Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
See the following commit in SDK:
commit 62a2fb4fd3001aefad9ec3b2e2e7c47e5b0f21e1
Author: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Date: Fri Jan 24 13:32:04 2020 +0900
Enable dummy transfer by SPI using DMA
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
