1. Configurable mapping of virtual address to psram physical address
2. Access SPIRAM memory at high physical address through bank switching
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Version 1.3.1 is the latest tagged version as of November
the 21st, 2023. This patch prepares the required changes
to make v1.3.1 work.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Enable CONFIG_DEV_SIMPLE_ADDRENV for all the qemu configs that used
the virtio driver to fix compile error when use the NuttX implemented
metal io read/write operations.
Becasue up_addrenv_pa_to_va() and up_addrenv_va_to_pa() are not
implemented by default.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Summary:
- Fixes a linker issue in https://github.com/apache/nuttx/pull/8244 by disabling compiler optimization.
- Adjusts CONFIG_DEFAULT_TASK_STACKSIZE to 4096 to ensure proper functioning of cxxtest.
Impact:
- The changes may slightly affect performance due to disabled optimizations
but are necessary for cxxtest stability.
Testing:
- Successfully tested on QEMU-8.1.2 with arm gcc 12.3.Rel1,
confirming resolution of the linker issue and stable operation of cxxtest.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
These values are board-specific properties that must be known on the application side.
Until now, these values had to be hardcoded on the application side.
1. If CONFIG_ESP32S3_PHY_INIT_DATA_IN_PARTITION and CONFIG_ESP32S3_SUPPORT_MULTIPLE_PHY_INIT_DATA are enabled,
PHY initialization data (PHY initialization data is used for RF calibration) will be loaded from a partition.
2. The corresponding PHY init data type can be automatically switched according to the country code,
China's PHY init data bin is used by default, country code can be modified through the wapi command: wapi country <ifname> <country code>.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
It also makes the code look more similar to the ESP32-S3 SPI flash
implementation by creating a common `esp32_spiflash_init` that is
responsible to create the SPI flash operation tasks. The function
intended to initialize the SPI flash partions was, then, renamed to
`board_spiflash_init`.
During PSRAM initialization and flash operations, the Cache needs to be disabled.
So all data and code for the aforementioned scope is required to be placed in Internal RAM.
After https://github.com/apache/nuttx/pull/11007/ was merged, the
path for some files changed, requiring the linker to be fixed to
make it run from the internal memory once again.
The LINUM-STM32H753BI is a board with RS485, RS232, SD Card, CAN,
SD Card, USB, Ethernet, LCD, etc.
Signed-off-by" Jorge Guzman jorge.gzm@gmail.com
ci: correction in nsh defconfig file of LINUM-STM32H753BI
Using up_textheap_memalign to allocate memory if arch support textheap
for loading section.
The default system heap does not support execution permissions,
so up_textheap_memalign allocation is required.
this patch can fix issue about #11043
update esp32 elf config:
remove -CONFIG_ARCH_USE_TEXT_HEAP=y becuase ARCH_CHIP_ESP32 select
ARCH_HAVE_TEXT_HEAP
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
CI test for fmemopen() function was added. The test was merged with
fopencookie interface test and merged into single test_stdio.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- migrated /README are removed from /boards
- there are a lot of READMEs that should be further converted to rst.
At the moment they are moved to Documentation/platforms and included in rst files
The STM32F401RC-RS485 is a board with RS485 support, SD Card, buttons,
leds, temperature sensor, adc and etc.
Signed-off-by: Rodrigo Sim rcsim10@gmail.com
File system CI test was not testing the correct behavior of scanf and just
checked whether program did not end with hard fault. This adds
functionality check and required configuration options to run FS test.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Scanf CI test was not testing the correct behavior of scanf and just
checked whether program did not end with hard fault. This adds
functionality check and required configuration options to run scanf
test.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
To compile arm64 NuttX, use the following command:
./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run，use the following command
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
test config: ./tools/configure.sh -l qemu-armv8a:nsh_smp
Pass ostest
No matter big-endian or little-endian, ticket spinlock only check the
next and the owner is equal or not.
If they are equal, it means there is a task hold the lock or lock is
free.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
we can mount a zipfile in nuttx use mount command like this:
mount -t zipfs -o /data/test.zip /zip
The zipfs is a read only file system,The advantage is that it
does not occupy additional space when reading the decompressed file.
When used, reading and decompression operations are simultaneous.
The known disadvantage is that when using seek to read forward,
it will reopen and cause slow speed problems.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
External JLink is required to program the board, so the console via RTT
is available anyway. It is much more convenient to use than soldering the
P4 connector and working with an external UART converter.
* build-globals.sh
- Only look in the nuttx for external symbols used when loading
dynamic shared objects
* include/elf64.h
- Correct the type of fields in the Elf64_Phdr structure
* libs/libc/dlfcn/lib_dlclose.c
- Distinguish between ET_DYN and other objects as the former
has both text and data in a single allocation to reserve
GOT offsets
* libs/libc/dlfcn/lib_dlopen.c
- Code formatting
* libs/libc/modlib/modlib_bind.c
- Distinguish between relocation entry sizes by section type
- Handle RELA style relocations
* libs/libc/modlib/modlib_globals.S
- Formatting fixes
- Symbols should not be weak - they exist or they don't
* include/nuttx/lib/modlib.h
- Add an inidcator to module_s to distinguish between ET_DYN and other
* libs/libc/modlib/modlib_load.c
- ET_DYN objects need to keep the relative displacement between the text
and data sections due to GOT references from the former to the latter.
This also implies that linking may require modification from the default
for the shared objects being produced. For example, default alignment may
mean nearly 64K of wasted space.
* libs/libc/modlib/modlib_unload.c
sched/module/mod_rmmod.c
- Distingusih between freeing of ET_DYN storage and other as the former
is a single allocation.
* libs/libc/modlib/mod_insmod.c
- Cater for ET_DYN objects having init and preinit sections
Fix:
```
riscv-none-elf-ld: sotest.o: ABI is incompatible with that of the selected emulation:
target emulation `elf64-littleriscv' does not match `elf32-littleriscv'
riscv-none-elf-ld: failed to merge target specific data of file sotest.o
```
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
'rcS' will case files that has duplicate name been replaced.
so on the Mac platform we use 'q' instead of 'r' to achieve an
effect similar to '-P'
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
The board-level GPIO support is different from the already existing
button and LEDC support because it enable us to register the GPIO
pins as devices in `/dev/gpioX`. Some applications are able to use
this interface to read and write the GPIO pins.
Documentation was added regarding its usage. Please check
`Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst`
to fix the following linker error:
/usr/bin/ld: nuttx.rel: in function `aes_encrypt_xform':
/github/workspace/sources/nuttx/crypto/xform.c:509: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_decrypt_xform':
/github/workspace/sources/nuttx/crypto/xform.c:514: undefined reference to `aes_decrypt'
/usr/bin/ld: nuttx.rel: in function `aes_setkey_xform':
/github/workspace/sources/nuttx/crypto/xform.c:519: undefined reference to `aes_setkey'
/usr/bin/ld: nuttx.rel: in function `aes_ctr_crypt':
/github/workspace/sources/nuttx/crypto/xform.c:566: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_ctr_setkey':
/github/workspace/sources/nuttx/crypto/xform.c:585: undefined reference to `aes_setkey'
/usr/bin/ld: nuttx.rel: in function `aes_ofb_encrypt':
/github/workspace/sources/nuttx/crypto/xform.c:694: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_ofb_setkey':
/github/workspace/sources/nuttx/crypto/xform.c:706: undefined reference to `aes_setkey'
/usr/bin/ld: nuttx.rel: in function `aes_cfb8_encrypt':
/github/workspace/sources/nuttx/crypto/xform.c:733: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_cfb8_decrypt':
/github/workspace/sources/nuttx/crypto/xform.c:751: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_cfb128_encrypt':
/github/workspace/sources/nuttx/crypto/xform.c:765: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_cfb128_decrypt':
/github/workspace/sources/nuttx/crypto/xform.c:781: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_gmac_setkey':
/github/workspace/sources/nuttx/crypto/gmac.c:135: undefined reference to `aes_setkey'
/usr/bin/ld: /github/workspace/sources/nuttx/crypto/gmac.c:143: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_gmac_final':
/github/workspace/sources/nuttx/crypto/gmac.c:195: undefined reference to `aes_encrypt'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1. the defconfig is based on nuttx/boards/sim/sim/configs/nsh/defconfig
2. make the option enabled by default that needed by open posix
testsuite, such as PTHREAD_SPINLOCK, FS_AIO, TESTING_LTP etc.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Some SD card connectors do not have separate card detection pin. In that
case card detection has to be done on CD/DAT3 data line. This means
software (i.e. architecture level driver) has to take care of pin
configuration switching (pin has to be set as data pin in case of
transfer and as interrupt card detection pin when there is no action
on data line).
This commit adds CD/DAT3 line card detection support for SAMv7 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The class device only handles descriptor information specific to the class,
and shared descriptor information is passed through parameters and
handled by the composite driver.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Provide initial support for audio through the I2S peripheral to the
CS4344 audio codec on ESP32-S3-DevKitC-1 board.
Please check documentation for usage examples.
A usbdev has only one serial string, so use a unique macro to control it.
For boards that enable board serial string using COMPOSITE_BOARD_SERIALSTR,
PL2303_BOARD_SERIALSTR, CDCACM_BOARD_SERIALSTR, USBADB_BOARD_SERIALSTR,
USBMSC_BOARD_SERIALSTR, and RNDIS_BOARD_SERIALSTR, they need to be replaced
with BOARD_USBDEV_SERIALSTR.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
SiFive document: "ECC Error Handling Guide" states:
"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."
Clean the cache at this early stage so no ECC errors will be flooding later.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
When I try to set priorities in certain programs, such as init_priority(HIGH_PRIORITY), I've noticed that during linking, there's no guarantee that the programs will be compiled in the sequence I've specified based on priority. This has led to some runtime errors in my program.
I realized that in the ld file, when initializing dynamic arrays, there's no assurance of initializing init_array.* before init_array. This has resulted in runtime errors in the program. Consequently, I've rearranged the init_array.* in the ld file of NuttX to be placed before init_array and added a SORT operation to init_array.* to ensure accurate initialization based on priorities during linking.
update LIBFDT to LIBC_FDT
update CONFIG_LIBFDT_DTC_VERSION to CONFIG_LIBC_FDT_DTC_VERSION
move dtc source code to fdt/dtc
move version_gen.h from apps/system/fdt to current dir
Signed-off-by: liaoao <liaoao@xiaomi.com>
This patch starts to implement the ability to build Meadow.OS for the Meadow F7 board with the NuttX mainline. It will be followed by more patches, progressively enabling full Meadow.OS functionality. This configuration is a work in progress.
The Meadow.OS source code is needed to build this configuration. Meadow.OS is being open-sourced under the Apache 2.0 license. A prototype of the source code release and integration with NuttX is at https://github.com/WildernessLabs/Meadow.OS/tree/prototype
This is the second revision of this patch, as the first one (https://github.com/apache/nuttx/pull/9997) was causing build issues on NuttX CI and was reverted.
This should only impact the Meadow F7 board configurations.
No testing to be done, as the configuration is under development.
Move SCU-specific ak09912 sensor into spresense board layer.
Rename a function name to register SCU sensor driver
from ak09912_register to ak09912_scu_register.
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
make debug print hex again add board include
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
remove ccache, add board memory map
remove board reset
Summary:
- I noticed that device discovery for virtio-mmio devices does not
work without bus=virtio-mmio-bus.x option. Without this option,
qemu assigns the virtio device into the virtio-mmio space
in reverse order automatically.
- To fix this issue, we must specify the correct numbers for the
target machines. (i.e. arm32/64->32, rv32/64->8)
Impact:
- None
Testing:
- Tested with qemu-7.2.4
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Decreasing the value may increase DQ/DQS window size. Keep the default value
(1) for the existing board configurations.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Adds a platform specific implementation for tickless schedular operation. This includes:
- Tickless operation for vexriscv cores.
- Tickless operation for vexriscv-smp cores.
- Ticked operation for vexriscv-smp cores.
Ticked operation for vexriscv core has been refactored.
Additional default configuration added to demonstrate operation.
Both tickless and ticked options use Litex timer0 for scheduling intervals. This is significantly faster than interfaceing with the risc-v mtimer through opensbi.
ESP32-S3 has only one 2.4 GHz ISM band RF module, which is shared
by Bluetooth and Wi-Fi, so Bluetooth can’t receive or transmit data
while Wi-Fi is receiving or transmitting data and vice versa.
Under such circumstances, ESP32-S3 uses the time-division
multiplexing method to receive and transmit packets.
