Commit Graph

64 Commits

Author SHA1 Message Date
anjiahao
172d467c26 arch:add faultmask register operation to armv7-m & armv8-m
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-01-05 23:17:43 +02:00
Xiang Xiao
e17b678a16 compiler.h: Rename inline_function to always_inline_function
reserve inline_function macro for inline keyword

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-07 10:24:04 +02:00
Xiang Xiao
d80c2d7419 arch/arm: Remove all lazy fpu related code
since it is broken and inefficient, and then removed by:
commit dc961baaea
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 14 18:07:14 2022 +0800

    arm/armv7-[a|r]: move fpu save/restore to assembly handler

    Save/Restore FPU registers in C environment is dangerous practive,
    which cannot guarantee the compiler won't generate the assembly code
    with float point registers, especially in interrupt handling

    Signed-off-by: chao.an <anchao@xiaomi.com>

commit 8d66dbc068
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 7 13:48:04 2022 +0800

    arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only

    Signed-off-by: chao.an <anchao@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-19 11:09:36 +03:00
Xiang Xiao
7c5b2e3305 arch/arm: Remove FAR and CODE from common/ and arm*/ folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-19 00:23:59 +03:00
chao.an
29005bd79f board/arch_fpu*: move arch_[get|cmp]fpu to common arch
rename the arch api:
arch_getfpu  -> up_saveusercontext
arch_cmpfpu  -> up_cmpfpu

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-18 22:22:16 +08:00
chao.an
7b9978883c arch/arm: optimize context switch speed
The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-15 23:03:51 +09:00
Xiang Xiao
0c7517e579 arch: Remove the duplicated syscall.h in each arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
25213c42a5 arch/arm: Remove the empty spinlock.h file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-25 09:18:53 +09:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-16 11:11:14 -03:00
chao.an
0a8d951837 arch/arm: correct the frame pointer register declare
In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-19 01:26:07 -07:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-07 09:20:10 -03:00
Alin Jerpelea
c39339a7a8 arch: arm: include: nxstyle fixes
nxstyle fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-22 19:28:38 -07:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
Gregory Nutt
e6af32c88f Run nxstyle against all files modified by PR 848 2020-04-22 21:36:41 +01:00
Nathan Hartman
679b4fbee2 arch: Fix included directed -> included directly
This typo had been copied and pasted into numerous irq and syscall
headers.
2020-04-05 22:31:15 +01:00
Xiang Xiao
68951e8d72 Remove exra whitespace from files (#189)
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
2020-01-31 09:24:49 -06:00
Valmantas Palikša
bc7566a83f arch/arm/include/armv7-m/syscall.h: ARM EABI specifies that the stack should be aligned by 8 on function calls, inside the function is not required to be aligned by 8. Since these functions call svc, compiler doesn't know that the svc is a function, therefore it does not do any stack management. This change pushes an even number of args to the stack and maintains an 8 byte alignment. I've checked the assembly and it doesn't cause any more overhead that the hand written assembly. 2019-12-16 09:10:08 -06:00
Gregory Nutt
545cfada38 This commit removes CONFIG_ARCH_INT_DISABLEALL. In the normal course of things, interrupts must occasionally be disabled using the up_irq_save() inline function to prevent contention in use of resources that may be shared between interrupt level and non-interrupt level logic. Now the question arises, if we are using BASEPRI to disable interrupts and have high priority interrupts enabled (CONFIG_ARCH_HIPRI_INTERRUPT=y), do we disable all interrupts except SVCall (we cannot disable SVCall interrupts). Or do we only disable the "normal" interrupts?
If we are using the BASEPRI register to disable interrupts, then the answer is that we must disable ONLY the "normal interrupts".  That is because we cannot disable SVCALL interrupts and we cannot permit SVCAll interrupts running at a higher priority than the high priority interrupts (otherwise, they will introduce jitter in the high priority interrupt response time.)

Hence, if you need to disable the high priority interrupt, you will have to disable the interrupt either at the peripheral that generates the interrupt or at the NVIC.  Disabling global interrupts via the BASEPRI register cannot effect high priority interrupts.
2019-08-09 10:52:35 -06:00
Gregory Nutt
c300f27130 arch/arm/include/armv7-m/nvicpri.h: In the 'normal' case, the priority of the SVCALL interrupt was the same as the priority of the high priority interrupt. This means that SVCALL interrupt processing can defer the high priority interrupt and result in the jitter in that interrupt response. Fix is to raise the priority of the high priority interrupt above the priority of the SVCALL interrupt. Suggested by Nathan Hartman. 2019-08-09 07:07:16 -06:00
Gregory Nutt
abf6965c24 Squashed commit of the following:
libs/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    syscall/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    wireless/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    Documentation/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    include/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    drivers/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    sched/:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    configs:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/xtensa:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/z80:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/x86:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/renesas and arch/risc-v:  Remove references to CONFIG_DISABLE_SIGNALS.  Signals can no longer be disabled.
    arch/or1k:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
    arch/misoc:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
    arch/mips:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
    arch/avr:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
    arch/arm:  Remove all references to CONFIG_DISABLE_SIGNALS.  Signals are always enabled.
2019-04-29 14:52:05 -06:00
Gregory Nutt
b1001b4e50 Update TODO list regarding non-queuing of signal actions; Add comments in code at areas where the issue applies. 2019-02-04 08:35:03 -06:00
Xiang Xiao
bda6d7f065 arch/arm/include/syscall.h: Add missing inclusion of arch/armv7-r/syscall.h for CortexR. 2019-01-26 07:43:31 -06:00
Xiang Xiao
9f408e9937 arch/arm/src/include/xxx/syscall.h: Align semi-hosting call style with other syscalls 2019-01-26 07:40:47 -06:00
Xiang Xiao
2e70eef767 arch/arm/include/armv-7m/irq.h and armv6-m/irq.h: Remove redundant conditioning on CONFIG_BUILD_PROTECTED 2019-01-26 07:04:15 -06:00
Dave Marples
d0cda60442 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
Gregory Nutt
0001607f71 arch/arm: (1) Add semihost support for syslog, (2) Add semihost support for HostFS 2018-08-23 08:00:07 -06:00
Gregory Nutt
5996d70883 Revise commit 09ccd43d61: That change had the subtle side-effect of unconditionally enabling interrupts in the primask. That may be what we want in most cases, but certainly not all. This does increse the size of the inline function by about 48-bits per instantiation. 2018-08-04 07:37:31 -06:00
Gregory Nutt
09ccd43d61 arch/arm/include/armv7-m, arch/arm/include/armv7-m, arch/arm/include/stm32f7: Add a configuration to enable workaround for r0p1 Errata 837070: Increasing priority usingwrite to BASEPRI does not take effect immediately.
This update is required to be serialized to the instruction stream meaning that after this update completes, it takes effect immediately and no exceptions of lower priority than the new boosted priority can pre-empt execution.  Because of this erratum, the priority boosting does not take place immediately, allowing the instruction after the MSR to be interrupted by an exception of lower priority than the new boosted priority. This effect is only limited to the next instruction. Subsequent instructions are guaranteed to see the new boosted priority.

This was raised in Bitbucket issue 113 from Vadzim Dambrouski.
2018-08-02 16:51:58 -06:00
Gregory Nutt
8bd9cfe038 Squashed commit of the following:
arch/arm:  Remove support for CONFIG_ARMV7M_CMNVECTOR.  It is now the only vector support available.  Also remove CONFIG_HAVE_CMNVECTOR.  That no longer signifies anything."
    arch/arm/src/stm32:  This commit removes support for the dedicated vector handling from the STM32 architecture support. Only common vectors are now supported.
2018-06-20 12:30:37 -06:00
Gregory Nutt
6230ab01b6 arch/arm/include/armv7-m: Last change requires inclusion of chip.h for definition. 2018-06-06 10:38:51 -06:00
Gregory Nutt
977d41d519 Based on a change recommended by Mark Shulte:
Signal handlers maybe run with interrupts enabled or disabled, depending on how the task the received the signal was blocked. (i.e.: If sem_wait() is called, then we disable interrupts, then block the currently running task). This could be dangerous, because user code would be running with interrupts disabled.

This change forces interrupts to be enabled in up_sigdeliver() before executing the signal handler calling up_irq_enable() explicitly.  This is safe because, when we return to normal execution, interrupts will be restored to their previous state when the signal handler returns.
2018-06-06 09:54:30 -06:00
Gregory Nutt
aae306e942 i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region. 2016-11-26 12:04:02 -06:00
Aleksandr Vyhovanec
472115eda9 ARMv7-M: Add support for the IAR compiler 2016-04-02 08:14:09 -06:00
Gregory Nutt
666cc280f4 Rename irqenable() to up_irq_enable(); rename irqdisable() to up_irq_disable() 2016-02-14 16:54:09 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
36726b1bc4 Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
Gregory Nutt
cbdafb96d5 Remove unused function setipsr. Cortex-M IPSR register is not writable 2015-09-23 08:38:32 -06:00
Gregory Nutt
29136e51cc Clean up and review of header files for conformance to standards 2015-06-12 19:26:01 -06:00
Gregory Nutt
f72079cc63 Update COPYING file with special license requirements for PPPD 2015-03-11 09:14:15 -06:00
Gregory Nutt
9bcdf974a0 Add new common lazy FPU state saving option for ARMv7-M. Not yet verified 2015-03-06 08:26:43 -06:00
Gregory Nutt
e11679acf8 Rename CONFIG_NUTTX_KERNEL to CONFIG_BUILD_PROTECTED; Partially integrate new CONFIG_BUILD_KERNEL 2014-08-29 14:47:22 -06:00
Gregory Nutt
8dd679e875 ARMv7-A: Add SYSCALL handling logic 2014-08-28 14:52:14 -06:00
Gregory Nutt
cbf0141d6c Add an ARMv7-A system call definition header file 2014-08-28 13:21:36 -06:00
Gregory Nutt
9e941f1195 Change bne to bne.n in irqrestore() 2014-05-22 09:01:25 -06:00
Gregory Nutt
25d4ff745b More trailing whilespace removal 2014-04-13 16:22:22 -06:00
Gregory Nutt
36ead78f07 ARMv6-M/ARMv7-M: Correct a register handling error in signal delivery (Kernel build mode only). Noted by Mike Smith. 2014-02-23 08:25:49 -06:00
Gregory Nutt
a8004f9e07 Fix major misthink in Cortex-M0 port: The Cortex-M0 has no BASEPRI register. We have to revert to using the nasty PRIMASK register 2013-04-16 18:00:59 -06:00
patacongo
3e7db57403 Rework of kernel build signal dispatch to user-space handlers
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5778 42af7a65-404d-4744-a932-0658087f49c3
2013-03-23 14:46:02 +00:00
patacongo
4d3d2f2112 A few fixes related to dispatched signals in kernel mode (there are still issues)
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5777 42af7a65-404d-4744-a932-0658087f49c3
2013-03-22 21:59:05 +00:00
patacongo
87bb6ceb5b Fix syscall parameter passing for the case where the number of parameters is >4
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5767 42af7a65-404d-4744-a932-0658087f49c3
2013-03-21 00:25:17 +00:00