Commit Graph

15004 Commits

Author SHA1 Message Date
Gregory Nutt
eb4fff5221 Minor updates from review of last PR. 2019-08-15 10:05:21 -06:00
David Sidrane
77c3a06fea Merged in david_s5/nuttx/master_h7 (pull request #995)
Master h7

* stm327f:Kconfig add depends on BBSRAM

* stm32h7:memorymap fix BBSRAM name

* stm32h7:Add BBSRAM support

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-15 15:42:48 +00:00
Gregory Nutt
17a4efe031 boards/arm/s32k1xx/s32k118evb: More build fixes. 2019-08-14 13:31:21 -06:00
Gregory Nutt
963031f42c arch/arm/src/s32k1xx: A few fixes. The build progresses further but still fails. 2019-08-14 12:40:51 -06:00
Pavel Pisa
50a333f55c arch/arm/src/lpc17xx_40xx/Make.defs: Cortex-M system reset is applicable to LPC17_40 too. 2019-08-14 11:03:52 -06:00
Pavel Pisa
810bf5e87a symtab/Makefile: When system wide locale is set (i.e. en_US.UTF-8) then 'read' is ordered after 'readdir' even if separator is set to quotation mark and key set to 2. When C locale is used result is correct. 2019-08-14 11:02:30 -06:00
Gregory Nutt
2a228e8650 Fleshs out a few more things needed to compile and build the S32K118EVB board configuration.
Squashed commit of the following:

    arch/arm/include:  Add interrupt IRQ numbers.
    tools/: Add support for the S32K1XX family.
2019-08-14 10:57:54 -06:00
Gregory Nutt
36d21a7a5b Clean up a some missed re-naming in the last slash and burn s32k1xx commit. 2019-08-13 19:14:50 -06:00
Gregory Nutt
e3468c8aad arch/arm/src/s32k1xx: Bring in Cortex-M0+ Systick and interrupt handling from samd2l2; bring in Cortex-M4F Systick and interrupt handling from LPC54xx. 2019-08-13 19:10:38 -06:00
Gregory Nutt
7be79b661c arch/arm/src/s32k1xx: Fix some sub-directory names. 2019-08-13 18:50:54 -06:00
Pavel Pisa
913de5e216 arch/arm/src/lpc17xx_40xx/lpc17_40_can.c: f BOARD_CCLKSEL_DIVIDER is not equal to 1 on LPC178x or LPC40xx then base clock rate is calculated incorrectly because CCLK frequency does not correspond to PLL0 clock which is used for PCLK. This is partially workaround solution. It would be probably better to define BOARD_PCLK_FREQUENCY even for LPC176x targets and use that to replace divisor by base_clock in up_dev_s. 2019-08-13 16:16:49 -06:00
Gregory Nutt
8405f6510c arch/arm/src/s32k1xx: Bring in the lpuart from i.MXRT. It is the same IP. 2019-08-13 15:00:41 -06:00
Gregory Nutt
cd49e6fbd7 arch/arm/src/imxrt: Fix some errors in the LPUART register defintion files. Correct naming of a function: up_earlyserialinit() should be imxrt_earlyserialinit(). Remove prototypes for non-existent serial initialization functions. 2019-08-13 14:59:59 -06:00
Gregory Nutt
ce90390146 arch/arm/src/s32k1xx/hardware/s32k1xx_rcm.h: Add RCM register definition file. 2019-08-13 12:45:15 -06:00
Gregory Nutt
a1db129027 arch/arm/src/s32k1xx/hardware/s32k1xx_crc.h: Add CRC register definition file. 2019-08-13 11:24:46 -06:00
Gregory Nutt
d9a3f2ac0e arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h and s32k1xx_ewm.h: Add WDOG and EWM register definition file. 2019-08-13 11:05:08 -06:00
Gregory Nutt
b6c72debcb arch/arm/src/s32k1xx/hardware/s32k1xx_dmamux.h: Add DMAMUX register definition file. 2019-08-13 10:23:07 -06:00
Gregory Nutt
248a2966c6 arch/arm/src/s32k1xx/hardware/s32k1xx_gpio.h: Add GPIO register definition file. 2019-08-13 10:06:13 -06:00
Gregory Nutt
3f7b908674 arch/arm/src/s32k1xx/hardware/s32k1xx_port.h: Add PORT register definition file. 2019-08-13 08:46:41 -06:00
Gregory Nutt
387bd5d070 arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h: Add SIM register definition file. 2019-08-12 18:12:21 -06:00
Gregory Nutt
bcfabcbe53 This commit brings the initial files for a port to the NXP S32K1xx family. This is very much a work in progress and is little more that a partial configuration/build environment and some S32K1xx register definition header files
Squashed commit of the following:

    arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h:  Add MCM register definition file.
    arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h:  Add memory map definition file.
    arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h:  Add CMU register definition file.
    arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h:  Add PCC register definition file.
    arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h:  Add SCG register definition file.
    arch/arm/src/s32k1xx:  Add initial Make.defs files.
    Basic configuration logic for the S32K1 family.
2019-08-12 12:12:58 -06:00
Anthony Merlino
e649d6c21e Merged in antmerlino/nuttx/stm32f7_progmem (pull request #989)
arch/arm/src/stm32f7: Exposes stm32_flash_xxx functions.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-10 18:36:46 +00:00
raiden00pl
5ed743d58a Merged in raiden00/nuttx_f334 (pull request #974)
Master

* Revert "Merged in yanqil-br/feature-multi_chan_pwm (pull request #973)"

    This reverts commit aef0e0b538.

* arch/arm/src/{stm32/stm32f7/stm32h7/stm32l4}/stm32_pwm.c: configure multi-channel duty only if channel specified. This allows you to update duty cycle for a single channel

* nucleo-f303re/configs: add basic NSH configuration

* nucleo-f303re/configs/pwm: enable console on UART2 and set entry point to nsh_main

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-10 15:14:19 +00:00
Gregory Nutt
0ed1a06016 arch/arm/include/cxd56xx/chip.h: The correction of commit c300f27130 must be applied to the CXD56xx too. 2019-08-10 08:33:47 -06:00
Yan Li
aef0e0b538 Merged in yanqil-br/feature-multi_chan_pwm (pull request #973)
multi-channel PWM with single chan selection

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-09 23:57:31 +00:00
Nathan Hartman
60f777b8f4 Fix various typos in documentation and comments. 2019-08-09 14:35:07 -06:00
Anthony Merlino
7eaa47072f Merged in antmerlino/nuttx/stm32f7-usart1-dma (pull request #972)
stm32f7: USART1_RXDMA is dependent on STM32F7_DMA2 not STM32F7_DMA1

Approved-by: David Sidrane <david.sidrane@nscdg.com>
Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-09 18:24:13 +00:00
Nathan Hartman
b417ed4b40 Tiva GPTM timers: Implement 16-bit PWM mode
arch/arm/src/tiva/Kconfig:
    Remove EXPERIMENTAL dependency on TIVA_TIMER16_PWM.

arch/arm/src/tiva/common/tiva_timerlib.c:
    Fix wrong 32/16-bit ifdef checks.
    Add tiva_pwm16_sel_event() to choose GPTMCTL.TnEVENT value.
    Implement tiva_pwm_mode16().
    tiva_timer16_setinterval(): Fix wrong check for TIMER16_MODE_ONESHOT
        and TIMER16_MODE_PERIODIC. Was comparing to config->cmn.mode
        which can never have those values. This prevented interrupts being
        enabled. Compare to timer->mode instead.
    Add tiva_timer16pwm_setperiodduty() to set initial period, duty cycle,
        and enable interrupts if requested in GPTM peripheral. Interrupts
        are not enabled in NVIC until tiva_timer16_start() is called.
    Add tiva_timer16pwm_setduty() to update duty cycle at any time.

arch/arm/src/tiva/hardware/lm/lm3s_timer.h,
arch/arm/src/tiva/hardware/lm/lm4f_timer.h,
arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h,
arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h:
    Add missing defines; make surrounding defines consistent.

arch/arm/src/tiva/tiva_timer.h:
    Add new TIMER_FLAG_* configuration flags to enable configuring the
    16-bit PWM feature. Extend type of "flags" in tiva_timer32config_s
    and tiva_timer16config_s from 8- to 32-bits to allow more flags.
2019-08-09 11:03:44 -06:00
Gregory Nutt
545cfada38 This commit removes CONFIG_ARCH_INT_DISABLEALL. In the normal course of things, interrupts must occasionally be disabled using the up_irq_save() inline function to prevent contention in use of resources that may be shared between interrupt level and non-interrupt level logic. Now the question arises, if we are using BASEPRI to disable interrupts and have high priority interrupts enabled (CONFIG_ARCH_HIPRI_INTERRUPT=y), do we disable all interrupts except SVCall (we cannot disable SVCall interrupts). Or do we only disable the "normal" interrupts?
If we are using the BASEPRI register to disable interrupts, then the answer is that we must disable ONLY the "normal interrupts".  That is because we cannot disable SVCALL interrupts and we cannot permit SVCAll interrupts running at a higher priority than the high priority interrupts (otherwise, they will introduce jitter in the high priority interrupt response time.)

Hence, if you need to disable the high priority interrupt, you will have to disable the interrupt either at the peripheral that generates the interrupt or at the NVIC.  Disabling global interrupts via the BASEPRI register cannot effect high priority interrupts.
2019-08-09 10:52:35 -06:00
Gregory Nutt
c300f27130 arch/arm/include/armv7-m/nvicpri.h: In the 'normal' case, the priority of the SVCALL interrupt was the same as the priority of the high priority interrupt. This means that SVCALL interrupt processing can defer the high priority interrupt and result in the jitter in that interrupt response. Fix is to raise the priority of the high priority interrupt above the priority of the SVCALL interrupt. Suggested by Nathan Hartman. 2019-08-09 07:07:16 -06:00
David Sidrane
786d3453a2 Merged in david_s5/nuttx/master_f7_eth (pull request #970)
stm32f7:ethernet add timeout on MAC reset

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-08 16:17:57 +00:00
Gregory Nutt
2730714774 Update more comments and README.txt files to reflect new organization of the boards/ sub-directory. 2019-08-08 09:17:04 -06:00
Gregory Nutt
240926c995 Beginning to update comments to reflect new organization of the boards/ sub-directory. 2019-08-08 08:46:54 -06:00
Gregory Nutt
eaaa73198b boards/Board.mk: Correct a simulator included path problem introduced by reorganization of arch/sim/src. 2019-08-08 07:17:43 -06:00
Nathan Hartman
2f0a3b6d75 arch/arm/src/tiva/common/tiva_timerlib.c: Fix one code error and some comment errors. tiva_timer16_setinterval(): Was DEBUGASSERTing on mode != TIMER16_MODE. Fixed to DEBUGASSERT on mode == TIMER16_MODE. 2019-08-07 18:58:45 -06:00
Gregory Nutt
c840ac2496 arch/sim: Even though the simulation has no chips, it needs to have CONFIG_ARCH_CHIP and chip sub-directories. Otherwise, we would have to treat it as a special case in the build system. 2019-08-07 16:05:00 -06:00
Augusto Fraga Giachero
a1f1adb878 arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c: Fix the initialization for DP83848x PHYs. The DP83848x requires the RMII mode to be manually enabled through the MII_DP83848C_RBR register. Before querying the speed and mode it should wait for the link to be established. 2019-08-07 09:22:50 -06:00
Augusto Fraga Giachero
41d3ef5f1b arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c: Follow the procedure listed in the LPC176x/5x User Manual when reading from and writing to the PHY's registers (section 10.11.14). I couldn't see any behavioral change after this commit, but nonetheless is a good practice to follow the manufacturer's recommended procedure. 2019-08-07 09:01:10 -06:00
Augusto Fraga Giachero
17518b4a7d arch/arm/src/lpc17xx_40xx/Kconfig: Add missing LPC17_40_PHY_CEMENT_DISABLE config to the lpc17xx Kconfig file. For some reason this config wasn't referenced anywhere else except in arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c. 2019-08-07 08:59:38 -06:00
Nathan Hartman
06f693965c Tiva: Fix errors in low-level timer support
arch/arm/src/tiva/common/tiva_timerlib.c:
* tiva_gptm_configure() and tiva_gptm_release(): Fix error: Was calling
  tiva_emac_periphrdy() instead of tiva_gptm_periphrdy().

arch/arm/src/tiva/tiva_timer.h:
* Fix error in "abcde" description of bit flag defines.
2019-08-07 07:35:37 -06:00
Nathan Hartman
162e2e1c65 arch/arm/src/tiva/common/tiva_timerlib.c: Fix minor errors in tiva_timerlib
Fix incorrect preprocessor conditionals related to Kconfig defines:
* CONFIG_TIVA_TIMER32_EDGECOUNT -> CONFIG_TIVA_TIMER16_EDGECOUNT
* CONFIG_TIVA_TIMER32_TIMECAP -> CONFIG_TIVA_TIMER16_TIMECAP
* CONFIG_TIVA_TIMER32_PWM -> CONFIG_TIVA_TIMER16_PWM
2019-08-06 17:09:42 -06:00
David S. Alessio
ced0dc1e16 arch/arm/src/armv7-m: Add ARMv7-M setjmp/longjump functions. 2019-08-06 15:59:19 -06:00
Markus Bernet
f1462d2a2f arch/arm/src/stm32h7: Fix UART7/8 typos. Fix bug in ETH_MACQTXFCR configuration. 2019-08-06 07:37:55 -06:00
David Sidrane
1881a7216e Merged in david_s5/nuttx/master_kinetis_i2c_fix_txfer (pull request #965)
kinetis:i2c transfer ensure correct result returned

kinetis_i2c_transfer released the mutex then fetched
   the state, this resulted in returning the correct
   results.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-05 20:31:34 +00:00
Gregory Nutt
615c0ea7ee Change naming configs/ to boards in comments, Documentation, etc. Still a few more to go. 2019-08-05 07:13:48 -06:00
Alin Jerpelea
a1c991d921 Merged in alinjerpelea/nuttx (pull request #963)
Move boards to boards folder

* boards: rename configs folder to boards

    This is the proposed layout after the change:

    boards: - folder containing board folders
            <board>: - name of each board
                    drivers: - extra drivers specific for platform
                    include: - header files for the boars
                    scripts: - extra scripts specific for platform
                        src: - board specific code
                      tools: - extra tools specific for platform
                    <config>: - board specific configuration(s)

    Note:
    <xxx> names are dependent on platform

    This is a logical change to aim to the arch layout but this is a
    huge change it should be done in several steps to lower the risk.

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* Kconfig: replace configs with boards

    The change is needed after the path change

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* Makefile: replace configs with boards

    The change is needed after the path change

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* Makefile.*: replace configs with boards

    The change is needed after the path change

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* Make.defs: replace configs with boards

    The change is needed after the path change

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* .sh: replace configs with boards

    The change is needed after the path change

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* .mk: replace configs with boards

    The change is needed after the path change

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* .c & .h: replace configs with boards

    The change is needed after the path change

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* .bat: replace configs with boards

    The change is needed after the path change

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-05 12:04:14 +00:00
Nathan Hartman
5f76eb1207 arch/arm/src/tiva: LM3S, LM4F, TM4C: Fix GPIO IRQ error, ports R, S, T. Preprocessor logic for CONFIG_TIVA_GPIOx_IRQS was setting/clearing port Q defines when it should act on ports R, S, T. gpioport2irq() was missing handling for port T. 2019-08-04 16:55:26 -06:00
Nathan Hartman
68d43d3679 Fix typos. 2019-08-04 14:50:28 -06:00
Kejun ZHOU
19b81899de Merged in zhoukejun/nuttx-rv32-vega-lite (pull request #962)
Rename the arch/risc-v/src/gap8/gap.h to arch/risc-v/src/gap8/gap8.h

Signed-off-by: zhoukejun <zhoukejun@outlook.com>

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-08-04 13:25:07 +00:00
Nathan Hartman
a36d49e975 arch/arm/src/tiva, include/nuttx/sensors: Reinstate TM4C qencoder driver and expand its ioctls.
arch/arm/src/tiva/Kconfig:
* Add TIVA_HAVE_QEI0, TIVA_HAVE_QEI1 as applicable to each ARCH_CHIP_TM4C12*.
* Add config TIVA_QEI, TIVA_HAVE_QEI0, TIVA_HAVE_QEI1.
* Add config TIVA_QEI0, config TIVA_QEI1.

arch/arm/src/tiva/common/tiva_qencoder.c:
* Rewrite tiva_qe_setup().
* Replace tiva_qe_ppr() with tiva_qe_resetatppr().
* Add tiva_qe_resetatmaxpos(), tiva_qe_resetatindex().

arch/arm/src/tiva/hardware/tiva_qencoder.h:
* Add missing definitions: SIGMODE_QUADRATURE, SIGMODE_CLK_AND_DIR, SWAP_NO_SWAP, SWAP_PHA_PHB.

arch/arm/src/tiva/tiva_qencoder.h:
* Rename TIVA QEI ioctl QEIOC_PPR to QEIOC_RESETATPPR.
* Add TIVA QEI ioctl identifiers QEIOC_RESETATMAXPOS, QEIOC_RESETATINDEX.

include/nuttx/sensors/qencoder.h:
* Increase QE_TIVA_NCMDS from 3 to 5.
2019-08-02 15:56:05 -06:00