Gregory Nutt
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fcbf89c6f6
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ARMv7-A: L2CC PL310 address filtering is an optional feature
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2014-07-25 19:46:09 -06:00 |
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Gregory Nutt
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a007fa3f5e
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ARMv7-A: Add missing L2CC PL310 bit definitions
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2014-07-25 19:41:35 -06:00 |
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Gregory Nutt
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e74f37445b
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rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well.
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2014-07-25 17:25:17 -06:00 |
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Gregory Nutt
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0a134f0158
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Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handling
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2014-06-21 09:55:09 -06:00 |
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Gregory Nutt
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40b7ddf68e
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SAMA5: FIQs should be disabled along with IRQs on most exeptions in most configuratinons. arm_decodefiq and arm_decodeirq are mutually exclusive and, hence, can use the same interrupt stack
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2014-06-20 18:49:01 -06:00 |
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Gregory Nutt
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c68d2532be
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SAMA5D4: Add support for secure/FIQ interrupts; SAIC supports need to be be enabled unconditionally
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2014-06-20 18:16:41 -06:00 |
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Gregory Nutt
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0a2133b57f
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SAMA5D4: Add partial support for secure interrupt controller (SAIC)
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2014-06-20 15:22:00 -06:00 |
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Gregory Nutt
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1636d7cb2f
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Ooops... last (cosmetic) changes were still in the editor
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2014-05-06 15:00:39 -06:00 |
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Gregory Nutt
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422a9c9bfd
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Optimized memcpy() functin for the ARMv7-A from David Sidrane
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2014-05-06 14:58:48 -06:00 |
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Gregory Nutt
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e4fd434a60
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Cosmetic update to comments and README files
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2014-04-24 12:44:30 -06:00 |
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Gregory Nutt
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0d2e525bd4
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Updated comments; minor correction in some naming
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2014-04-23 14:46:39 -06:00 |
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Gregory Nutt
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9d12aa82fe
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Sourceforge Patch #37: Missing semicolon
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2014-04-16 09:43:34 -06:00 |
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Gregory Nutt
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25d4ff745b
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More trailing whilespace removal
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2014-04-13 16:22:22 -06:00 |
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Gregory Nutt
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c708eff608
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Make sure that there is one space after for
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2014-04-12 13:28:22 -06:00 |
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Gregory Nutt
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78607a7ea9
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SAMA5: Don't use MMU PMD bufferable bit to try to control write-through vs write-back. It does not work that way
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2014-04-04 16:05:20 -06:00 |
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Gregory Nutt
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489651d041
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ARMv7-A: Typo fix from David Sidrane
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2014-04-03 15:43:13 -06:00 |
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Gregory Nutt
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362d539914
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If LOWVECTORS is selected, then we need to clear the VBAR register. A bootloader may have left the VBAR in an bad state
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2014-04-03 13:09:30 -06:00 |
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Gregory Nutt
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e3d2117b29
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SAMA5: Make sure the MMU and caches are disabled on power up; flush the vector region D-Cache after copying interrupt vectors; make sure that D-Cache, I-Cache, and TLBs are invalidated after modifying the AXI MATRIX remapping
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2014-04-02 16:27:00 -06:00 |
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Gregory Nutt
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7372485e16
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Updated comments and README
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2014-04-02 09:03:29 -06:00 |
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Gregory Nutt
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5ac5506b35
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All ARM assertion logic will show stack usage on assertion if DEBUG_STACK is enabled
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2014-03-23 10:06:48 -06:00 |
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Gregory Nutt
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5b9f1f54c2
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Add option to dump buffered USB trace data on an assertion
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2014-03-20 10:56:30 -06:00 |
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Gregory Nutt
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306271d151
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Buildroot EABI (vs OABI) is now the default
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2014-02-28 07:49:15 -06:00 |
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Gregory Nutt
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6e6b048e5a
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SAMA5: Fix logic for running with data in SDRAM
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2014-01-29 07:49:23 -06:00 |
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Gregory Nutt
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e29e0f1cc4
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ARMv7-A: Conditionally compile out more unneeded logic when .data and .bss are in SDRAM
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2014-01-28 16:39:08 -06:00 |
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Gregory Nutt
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93bd80b080
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SAMA5: Mostly cosmetic
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2014-01-28 15:54:03 -06:00 |
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Gregory Nutt
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c930554c2c
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Add support for .data and .bss in SDRAM
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2014-01-28 14:35:03 -06:00 |
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Gregory Nutt
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a26b03d0d0
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rename up_led*() functions to board_led_*()
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2014-01-24 14:28:49 -06:00 |
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Gregory Nutt
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231889c888
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The optimization level can now be selected as part of the configuration
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2014-01-24 07:45:35 -06:00 |
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Gregory Nutt
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363d44b7d0
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Cosmetic spaces to tabs change
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2013-12-08 10:38:33 -06:00 |
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Gregory Nutt
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c131e94d04
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Add more nops after enabling MMU for Cortex-A8
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2014-01-07 08:38:00 -06:00 |
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Gregory Nutt
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f1e44300c6
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A10: Fix error in IRQ dispatch; vector table seems to be offset by 64 bytes?
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2013-12-07 08:36:30 -06:00 |
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Gregory Nutt
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e86f940374
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SVC is the preferred mnemonic vs. SWI for cortex A
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2014-01-05 16:21:41 -06:00 |
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Gregory Nutt
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1705b3f894
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Fix some missing parameters in macros
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2013-12-22 16:29:36 -06:00 |
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Gregory Nutt
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d28622a628
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Replace explicit hex MMU value with definition
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2013-12-18 12:47:43 -06:00 |
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Gregory Nutt
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9462db3d3c
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A10: Extend register debug logic
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2013-12-18 11:26:48 -06:00 |
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Gregory Nutt
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b48685b34b
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Cortex-A: Fix start-up cache invalidation logi
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2013-12-18 09:01:43 -06:00 |
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Gregory Nutt
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9ab637d218
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Remove executable mode bits
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2013-11-17 08:27:11 -06:00 |
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Gregory Nutt
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77c2cf2aa8
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Cosmetic changes to comments and README files
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2013-12-16 13:48:20 -06:00 |
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Gregory Nutt
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05d6d3c252
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Trivial updates to comments and README files
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2013-12-16 11:13:55 -06:00 |
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Gregory Nutt
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ccd5763003
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Review Cortex-A9 CP15 registers and update register definitions
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2013-12-16 10:23:29 -06:00 |
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Gregory Nutt
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0ef05b06d7
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ARMv7-A: If the page table does not like in same address range as .text and primary RAM, then we will need to set up an additional mapping for the page table at boot time.
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2013-12-16 08:26:07 -06:00 |
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Gregory Nutt
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04de5c4452
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Port IDLE/interrupt stack coloration to ARM and ARMv7-A architectures
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2013-11-01 15:30:18 -06:00 |
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Gregory Nutt
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b8085906b9
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Extend stack debug logic to include IDLE and interrupt stacks. Also color the heap as well. Based on suggestions from David Sidrane
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2013-11-01 11:16:51 -06:00 |
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Gregory Nutt
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98ffd096a0
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SAMA5 LCDC: Correct how framebuffer memory was being mapped; Remove options to get framebuffer memory in various. Because of the mapping and aligment requirements, those options really cannot be supported
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2013-10-13 13:08:05 -06:00 |
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Gregory Nutt
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245f5ad32d
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Slightly improved debug output
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2013-09-24 13:47:03 -06:00 |
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Gregory Nutt
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b2e3a95565
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Un-neccesary, cosmetic changes to label names and comments
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2013-09-22 08:54:06 -06:00 |
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Gregory Nutt
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d1ac44242f
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ARMv7-A: Fix some error in alignment to cache line boundaries in the cache operations
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2013-09-21 15:47:00 -06:00 |
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Gregory Nutt
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c9050ae5fd
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ARMv7-A: Clarify end address paramet in cache operations: It is the end+1 address, not the end address
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2013-09-21 12:16:34 -06:00 |
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Gregory Nutt
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56f9092a87
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Fix all occurrences of "the the" in documentation and comments
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2013-08-27 09:40:19 -06:00 |
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Gregory Nutt
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b00d72a7f2
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SAMA5: More MMU-related changes to properly initialize SDRAM
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2013-08-02 11:11:57 -06:00 |
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