Petro Karashchenko
c0881feca9
boards/arm/samv7/same70-qmtech: fix description in README.txt
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-23 20:08:10 -03:00
Petro Karashchenko
311f351da5
boards/arm/samv7/same70-qmtech: enable slow crystal
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-23 22:00:45 +01:00
Huang Qi
71d3ff1045
arch/risc-v: Remove g_serial_ok
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`WFI` is enough to wait the ready signal from master core,
so we can remove it.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00
Huang Qi
422e005183
arch/risc-v: Move xxx_cpustart.c to common
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It's a common solution for MSIP and IPI based risc-v smp soc,
also works on qemu-rv smp (WIP).
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00
Norman Rasmussen
da5659138b
Fix regression where used code was marked as unused
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Commit 5d1a444812
replaced __attribute__
((unused)) with unused_code but two instances of __attribute__ ((used))
were also incorrectly replaced. Add used_code/used_data and used them
instead.
2022-01-23 14:57:19 +08:00
raiden00pl
4c2dd3924a
include/nuttx/can.h: rename CAN_ERR_CTRL to CAN_ERR_CRTL for compatibility with libcanutils
2022-01-23 01:34:34 +08:00
raiden00pl
7d39642561
include/nuttx/can.h: make SocketCAN error definitions always available
2022-01-23 01:34:34 +08:00
Petro Karashchenko
6c27f3c19d
toolchain: add libm to EXTRA_LIBS only if it is provided by the compiler
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Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 15:36:29 +08:00
Alexander Lunev
f73abc76d5
sim/netdev: retrieve all the queued RX frames from the network device on every poll.
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As a result, the RX throughput is increased significantly w/o harming the TX throughput.
2022-01-22 15:34:58 +08:00
Xu Xingliang
021363f1db
driver/mmcsd: add option to limit block count in multiple-block transfer mode.
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Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
2022-01-22 14:59:26 +08:00
Petro Karashchenko
d611e2d99b
risc-v/mpfs: switch to NuttX types for opensbi
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 14:58:56 +08:00
Petro Karashchenko
ea177faaf6
boards/same70-qmtech: clarify usage of CD signal on SD card connector
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By default SAME70_QMTECH board does not have CD signal routed to
SAME70. The HW rework can be done to enable CD signal. Clarify
description of SD card connector.
Change configuration of CD pin to get auto unmount work correctly
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 14:57:36 +08:00
Huang Qi
b803919b9d
arch/risc-v: Merge mcause.h into irq.h
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-22 14:57:05 +08:00
Alexander Lunev
eec94132c4
net/tcp/sendfile: removed excessive overwrites of conn->sndseq
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(conn->sndseq was updated in multiple places that was unreasonable and complicated).
This optimization is the same as it was done for tcp_send_unbuffered.
2022-01-22 00:43:53 +08:00
Jukka Laitinen
9061c92ec8
arch/risc-v/src/mpfs: Make each hart entry configurable for bootloader
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Add two config flags for each hart for a bootloader nuttx:
CONFIG_MPFS_HARTx_SBI :
- select whether the hart boots via opensbi or not.
CONFIG_MPFS_HARTx_ENTRYPOINT :
- the target address to jump to, either directly from startup code or
from SBI if CONFIG_MPFS_HARTx_SBI is set
This allows building a nuttx based bootloader application, which can load
different applications/OSs for individual harts and jump to those
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-22 00:43:05 +08:00
Jukka Laitinen
36b73fd0a3
arch/risc-v/src/mpfs/mpfs_opensbi.c: Ensure stack alignment of 16 bytes
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Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-22 00:43:05 +08:00
Alexander Lunev
338b122b2b
net/tcp/sendfile: fixed an issue with unackseq calculation.
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Wrong unackseq calculation locked conn->tx_unacked at non-zero values
even if all ACKs were received.
This issue is the same as it was with tcp_send_unbuffered.
2022-01-22 00:42:29 +08:00
Alexander Lunev
c9e32dd4a4
tcp: fixed warning: ISO C90 forbids mixed declarations and code
2022-01-22 00:41:42 +08:00
Eero Nurkkala
2a22c0e32d
risc-v/mpfs: OpenSBI: utilize an index2id table
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Hart index to hart id table is used to track unused and used harts. This
table is useful when configuring only some of the harts for OpenSBI use.
Mpfs will always have the hart0 unused, so mark it with -1.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-21 13:40:58 -03:00
Abdelatif Guettouche
8c582c27b8
esp32c3_irq.c: Add a comment explaining the assigment of CURRENT_REGS to
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regs.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-22 00:38:43 +08:00
Abdelatif Guettouche
e335d44028
esp32c3_irq.c: Skip over ECALL instruction.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-22 00:38:43 +08:00
zouboan
a310b0952f
bug patch for frexpf function
2022-01-21 13:37:37 -03:00
Petro Karashchenko
a32381ca32
Revert "risc-v/mpfs: switch to NuttX types for opensbi"
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This reverts commit 1dccc374ab
.
2022-01-21 21:38:31 +08:00
YAMAMOTO Takashi
f356ff34a7
arch/sim/src/sim/up_macho_init.c: Fix an assertion
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Handle the case of no constructors.
2022-01-21 11:01:53 +01:00
Petro Karashchenko
1dccc374ab
risc-v/mpfs: switch to NuttX types for opensbi
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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-21 17:12:22 +08:00
zouboan
0342272e5a
up_progmem_erasesize for stm32f20xxf40xx_flash.c
2022-01-21 14:57:32 +08:00
Huang Qi
d846bb0235
arch/risc-v: Remove dupped irq code from mpfs
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
6dc4dd207f
arch/risc-v: Remove dupped irq code from rv32m1
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
089dc2e090
arch/risc-v: Remove dupped irq code from litex
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
d1edd887d5
arch/risc-v: Remove dupped irq code from c906
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
bd57229f3c
arch/risc-v: Remove dupped irq code from bl602
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
8532feda78
arch/risc-v: Remove dupped irq code from fe310
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
e81439a367
arch/risc-v: Remove dupped irq code from k210
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
7738bb98fc
arch/risc-v: Remove dupped irq code from qemu-rv
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
f43d677c2e
arch/risc-v: Unify common irq code to arch/irq.h
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Xiang Xiao
2935751bfd
Fix error: implicit declaration of function 'up_cpu_index'
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
aa2cdcd848
xtensa/esp32: Change "cpu <= CONFIG_SMP_NCPUS" to "cpu < CONFIG_SMP_NCPUS"
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
77792a1598
sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case
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to simplify the SMP related code logic
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
04297c3ca3
board: Remove -fno-omit-frame-pointer from Make.defs
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except sim arch, since this flag is set inside Toolschain.defs now
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Xiang Xiao
c5c50acb93
board: Remove -fstrict-volatile-bitfields
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Xiang Xiao
3e28192b2f
board/bl602: Remove -fshort-enums
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Xiang Xiao
a9e4c6ace1
libc: backtrace_malloc change sprintf to snprintf
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since snprintf can handle NULL pointer but sprintf can't.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 14:33:29 +01:00
Ville Juven
0a1a1e9b79
Fix user PGT flags (don't map them globally)
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A global mapping means it exists in all address environments. Only
kernel mappings should be mapped as global.
2022-01-20 20:30:13 +08:00
Ville Juven
56ade25f31
Add pte getter to RISC-V MMU driver
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Like the title says, a getter to read one PTE.
2022-01-20 20:30:13 +08:00
Ville Juven
c4b3672937
RISC-V MMU driver: fix region setting for L1/L2 page tables
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The region setting worked for L3 (Sv39) entries only. This fixes the
procedure so that L1 (Gigapages) or L2 (Megapages) can be also set
with it.
2022-01-20 20:30:13 +08:00
Ville Juven
e676d2985d
Present common MMU flags in common MMU driver header
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Flags to use for intermediate page tables, as well as leaf entries
2022-01-20 20:30:13 +08:00
Ville Juven
33435e76da
Changes to Sv39 MMU driver public header
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- Define RV_MMU_PT_LEVELS as the arch max
- Add way to find the PPN from a PTE
- Make utility function to create a satp register value, instead of
combining this to mmu_enable
- Add function to read the current satp value
- Add function to write the satp register, also fix the fence instruction
2022-01-20 20:30:13 +08:00
Ville Juven
926a19217e
Add simple MMU driver for RISC-V (Sv39)
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Sv39 is the only mode supported for now. However, it should be trivial
to extend the driver to support the other modes (including Sv32) as well.
The driver is tested with mpfs only, but it should work with any riscv
implementation.
2022-01-20 20:30:13 +08:00
Juha Niskanen
2b63b811e0
libs/libc/misc/lib_execinfo.c: fix bad memory access
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Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2022-01-20 18:58:40 +08:00
Alexander Lunev
64dd669749
net/tcp/sendfile: retransmit only one the earliest not acknowledged segment
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(according to RFC 6298 (5.4)). The issue is the same as it was in tcp_send_unbuffered.c.
2022-01-20 18:37:39 +08:00