Gregory Nutt
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2de3781ebf
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Slightly improved debug output
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2013-09-24 13:47:03 -06:00 |
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Gregory Nutt
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8a1e33cb10
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Un-neccesary, cosmetic changes to label names and comments
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2013-09-22 08:54:06 -06:00 |
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Gregory Nutt
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9cb23c5ccb
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ARMv7-A: Fix some error in alignment to cache line boundaries in the cache operations
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2013-09-21 15:47:00 -06:00 |
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Gregory Nutt
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c900c580ae
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ARMv7-A: Clarify end address paramet in cache operations: It is the end+1 address, not the end address
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2013-09-21 12:16:34 -06:00 |
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Gregory Nutt
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bc46b447dc
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Fix all occurrences of "the the" in documentation and comments
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2013-08-27 09:40:19 -06:00 |
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Gregory Nutt
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2feb83a2f8
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SAMA5: More MMU-related changes to properly initialize SDRAM
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2013-08-02 11:11:57 -06:00 |
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Gregory Nutt
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b148465beb
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ARMv7-A: Map all of .text, .bss, .data., stacks before enabling the MMU and caching. This is simpler and avoids fears I have about caching
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2013-08-01 10:05:33 -06:00 |
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Gregory Nutt
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f2195a16b2
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ARMv7-A: Separate CONFIG_PAGING start-up logic into a different startup file. Too much conditional compilation.
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2013-08-01 07:41:00 -06:00 |
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Gregory Nutt
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fde3777e9e
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Fix Cortex-A CPSR register field definition
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2013-07-30 19:05:24 -06:00 |
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Gregory Nutt
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8bfdf70766
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ARMv7-A: Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM
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2013-07-30 13:20:33 -06:00 |
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Gregory Nutt
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413aba0bf5
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SAMA5: More cache and mmu inline utility functions
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2013-07-29 19:57:15 -06:00 |
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Gregory Nutt
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36b1cd0a6b
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SAMA5: Separate cache operations into separate files
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2013-07-29 18:38:02 -06:00 |
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Gregory Nutt
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5351598323
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Changes to ARMv7-A boot logic to handle the case where we execute out of NOR FLASH
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2013-07-29 17:54:56 -06:00 |
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Gregory Nutt
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4ba648aaae
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SAMA5: Add file structure to support board-specific initialization of NOR flash
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2013-07-29 07:41:53 -06:00 |
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Gregory Nutt
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9a94a3707c
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SAMA5: The ostest configuration have been converted to run out of NOR flash. There is more to be done, however
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2013-07-28 15:07:35 -06:00 |
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Gregory Nutt
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7dc8dd4b50
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SAMA5: Correct a clock configuration bug; clarify some MMU memory types
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2013-07-28 12:44:06 -06:00 |
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Gregory Nutt
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263678e05b
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SAMA5: Correct vector mapping
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2013-07-28 09:44:11 -06:00 |
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Gregory Nutt
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f0e3011fc3
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Removed unused ARMv7-A cache function
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2013-07-27 14:03:02 -06:00 |
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Gregory Nutt
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efa21b82bc
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SAMA5: Fix heap allocation bugs
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2013-07-27 11:28:31 -06:00 |
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Gregory Nutt
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c4ec723089
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SAMA5 page table is cached; need to flush the cache each time that the page table is updated
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2013-07-27 09:27:37 -06:00 |
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Gregory Nutt
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6fc4b9aacc
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Correct an error in Cortex-A5 intermediate MMU mapping
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2013-07-26 17:26:53 -06:00 |
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Gregory Nutt
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dc92037e67
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Add a hello world configuration to help with the SAMA5 bringup
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2013-07-26 15:28:01 -06:00 |
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Gregory Nutt
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70f0ffdfc5
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Finally... renamed all CONFIG_DRAM_ settings to CONFIG_RAM_
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2013-07-26 10:09:17 -06:00 |
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Gregory Nutt
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ec8a56259c
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SAMA5: If the page table is in high memory, make sure that it is excluded from the heap
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2013-07-26 09:16:46 -06:00 |
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Gregory Nutt
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49f9b7040e
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Misc Cortex-A5 MMU-related fix -- still does not boot
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2013-07-25 16:37:55 -06:00 |
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Gregory Nutt
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55df28dbcf
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Fix an uninitialized register error that crept into the ARM9 start up code many years ago and was recently cloned into the Cortex-A5. Obviously no on has used NuttX with ARM9 for years
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2013-07-24 20:12:04 -06:00 |
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Gregory Nutt
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e6beda428a
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Fix SAMA5 vector linking issue
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2013-07-24 12:51:42 -06:00 |
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Gregory Nutt
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77e1c27005
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Update SAMA5D3x-EK board configuration to support on-board UART connections, LEDs, and push buttons
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2013-07-24 12:27:12 -06:00 |
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Gregory Nutt
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3860fc17f0
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Improve Cortex-A5 context switching so that a little less copying is done
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2013-07-24 07:47:51 -06:00 |
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Gregory Nutt
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d6ae8db987
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ARMv7-N: Fix a copy error introduced in the previous check-in
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2013-07-23 19:09:17 -06:00 |
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Gregory Nutt
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535048a73c
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Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A
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2013-07-23 17:52:06 -06:00 |
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Gregory Nutt
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812bf02972
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ARMv7-A: Need 8-byte stack alignment when callign C code from interrupt handlers. This change needs to be ported to other ARM architectures as well
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2013-07-23 14:47:16 -06:00 |
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Gregory Nutt
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1350b2a576
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SAMA5 interrupt handling logic
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2013-07-22 11:54:39 -06:00 |
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Gregory Nutt
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5bbc86f894
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SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable. Add skeleton file for SAMA5 interrupt management. Also change from last commit that was left in the editor
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2013-07-21 17:08:40 -06:00 |
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Gregory Nutt
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543b5b7e03
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A few more Cortex-A5 and SAMA5 files
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2013-07-21 12:52:38 -06:00 |
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Gregory Nutt
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66259bfc53
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Misc Cortex-A5 changes include new file for cache operations
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2013-07-20 13:06:00 -06:00 |
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Gregory Nutt
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b26d5c7164
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A few more SAMA5D3 files
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2013-07-19 17:45:28 -06:00 |
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Gregory Nutt
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5356bd1bbd
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More ARMv7-A files that are just copies of the ARMv4/5 files for now
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2013-07-19 11:43:04 -06:00 |
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Gregory Nutt
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8f2ad7eec1
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Some initial frame for Cortex-A5 support. No much yet
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2013-07-18 15:20:47 -06:00 |
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