Commit Graph

18785 Commits

Author SHA1 Message Date
zhuyanlin
f5d180bbdf xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO
For up_irq_disable, use XCHAL_EXCM_LEVEL
For up_irq_save,  use XCHAL_IRQ_LEVEL.
Then we can use svcall in enter_crritical_section.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-25 20:43:03 +08:00
Huang Qi
e8552156b6 arch/risc-v: Remove unneeded ISA specifc interface
They are not really defined and used in any where:
uint32_t up_getmisa(void);
uint32_t up_getarchid(void);
uint32_t up_getimpid(void);
uint32_t up_getvendorid(void);
uint32_t up_gethartid(void);

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Huang Qi
cfed970633 arch/misoc: Correct gurad macro for irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Huang Qi
8b66280b4f arch/risc-v: Update outdated comments
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Gustavo Henrique Nihei
ea1b49119a xtensa/esp32s3: Apply minor fixes to documentation and code style
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 10:51:25 +08:00
Gustavo Henrique Nihei
add99fead3 xtensa/esp32s3: Add support for Oneshot timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 10:51:25 +08:00
Masayuki Ishikawa
de95a8550f arch, board: Add thumb support to i.MX6
Summary:
- This commit adds thumb support to i.MX6
- Also, applies the same coding style to arch_elf.c

Impact:
- i.MX6 only

Testing:
- Tested with sabre-6quad:smp (QEMU, Dev board)
- Tested with sabre-6quad:netnsh (QEMU)
- Tested with sabre-6quad:netknsh (QEMU, not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-25 10:51:12 +08:00
Xiang Xiao
25213c42a5 arch/arm: Remove the empty spinlock.h file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-25 09:18:53 +09:00
Abdelatif Guettouche
dc130b4830 arch/xtensa/esp32s2_irq.c: Correctly enable the software interrupt.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-25 08:55:41 +09:00
Gustavo Henrique Nihei
b49ee3d4ed xtensa/esp32s3: Add support for Main System Watchdog Timers
Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 02:13:00 +08:00
Anton Potapov
9603b8f67c Add DAC2 configuration for stm32f405. 2022-02-24 12:09:41 -05:00
Gustavo Henrique Nihei
3400b42a33 xtensa/esp32: Fix a minor typo in documentation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-24 17:43:39 +01:00
Gustavo Henrique Nihei
a5024a707d xtensa/esp32s3: Use the running CPU ID for enabling internal interrupts
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-24 17:43:39 +01:00
Gustavo Henrique Nihei
83f3ba6d22 xtensa/esp32s3: Add support for Timer Groups 0 and 1
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 00:13:34 +08:00
zhuyanlin
7d350204f0 xtensa: fix XTHAL_REL_LE not find
fix `XTHAL_REL_LE` not find build break

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 22:13:46 +08:00
Xiang Xiao
6fa5885d2d arch/esp32: Update esp-wireless-drivers-3rdparty to verion 45701c0
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 09:05:40 +01:00
zhuyanlin
fc9791c269 xtensa:esp32s3: setup software interrupt as swi interrupt.
Enable and setup software interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 00:06:43 +01:00
zhuyanlin
bf40d70df9 xtensa:esp32s2: setup software interrupt as swi interrupt
Enable and setup software interrupt for esp32s2

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 00:06:43 +01:00
zhuyanlin
7b32ce190e xtensa:esp32: setup software interrupt. (bit 29)
Enable and setup software interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 00:06:43 +01:00
Xiang Xiao
d7fe0127b0 Replece clock_gettime(CLOCK_REALTIME) with clock_systime_timespec if suitable
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 01:06:36 +08:00
Xiang Xiao
43f57240e0 Replece clock_gettime(CLOCK_MONOTONIC) with clock_systime_timespec
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 01:06:36 +08:00
chao.an
13889ba868 arch/arm: unify some duplicate code to common layer
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 21:35:55 +08:00
chao.an
6cc0aaf5b9 arch/arm: unify switch context from software interrupt
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 15:04:29 +09:00
chao.an
db3a40ac25 arch/armv7-r: unify switch context from software interrupt
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 15:04:29 +09:00
chao.an
61cd9dfca1 arch/armv7-a: unify switch context from software interrupt
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 15:04:29 +09:00
Gregory Nutt
1ded8bbabb Garbage configuration setting in EFM32 code
arch/arm/src/efm32/efm32_start.c:

      /* For the case of the separate user-/kernel-space build, perform whatever
       * platform specific initialization of the user memory is required.
      * Normally this just means initializing the user space .data and .bss
       * segments.
       */

    #ifdef CONFIG_NUTTX_KERNEL
      efm32_userspace();
      showprogress('E');
    #endif

But there is no CONFIG_NUTTX_KERNEL configuration setting.  Comparing this to other architectures it is clear this should be

    #ifdef CONFIG_BUILD_PROTECTED
2022-02-23 03:40:44 +08:00
Xiang Xiao
f1ed349dd9 sched/clock: Remove CLOCK_MONOTONIC option from Kconfig
here is the reason:
1.clock_systime_timespec(core function) always exist regardless the setting
2.CLOCK_MONOTONIC is a foundamental clock type required by many places

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-23 01:21:26 +08:00
zhuyanlin
7b00c8bdb8 arch:xtensa: modify svcall to swint
Reason: xtensa svcall only have level-1 interrupt level.
Sush do not generate interrupt when up_irq_save.
Software int can generate interrupt when up_irq_save.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-22 14:06:24 -03:00
chao.an
0aa0022b12 arch/armv7-a: replace SYS_signal_handler_return hardcode
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-22 17:59:02 +08:00
chao.an
e0fabbfdd6 arch/arm: replace SYS_syscall_return hardcode from syscall
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-22 17:59:02 +08:00
Xiang Xiao
2f24d2c265 arch/ceva: Replace OUTDIR with TOPDIR
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-21 09:25:26 +01:00
Xiang Xiao
163fe4ff0b boards: Replace CONFIG_CYGWIN_WINTOOL with CONVERT_PATH
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 21:15:36 +01:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 20:10:14 +01:00
Oki Minabe
e9a94a003d old arm: add BUILD_KERNEL code in arm/arm_vectors.S 2022-02-20 21:03:54 +09:00
Oki Minabe
19e5c8f6d3 armv7-a/r: fix SVC's sp restore in arm_vectors.S 2022-02-20 18:39:30 +08:00
Xiang Xiao
d29f3bd21c arm/rtl8720c: Remove the unused Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 04:15:34 +01:00
Huang Qi
da25883c64 arch/sim: Fix usrsock build break on macOS
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 09:06:46 -03:00
chao.an
5da5ffb7d4 sim/usrsock: correct the xid type to uint64_t
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-18 08:16:17 +01:00
Abdelatif Guettouche
ab18b7b3d3 esp32xx_irq.c: Fix CPU interrupt documentation to remove the MAC
interrupt from the internal interrupt table.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
ee88235d81 esp32_irq.c: Don't reserve BT and Wifi CPU interrupts for APP CPU as
they are attached to the PRO CPU.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
17e43b0b4a esp32_irq.c: For internal interrupts use the current CPU to enable them.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
3d2771c49a esp32_irq.c: Move interrupt initialisation for special drivers to
`up_irqinitialize`.  `esp32_cpuint_initialize` is not a good place as
it's also called from CPU1.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Huang Qi
0c5aff9be6 risc-v/qemu-rv: Supports SMP up to 8 cores
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
Huang Qi
36ff081b1a risc-v: Support more than 2 cores in riscv_cpu_boot
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
Huang Qi
7c18290331 risc-v: Rename up_fault to riscv_fault
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
lp.xiao
bc12260540 dp83848c ethernet phy interrupt support 2022-02-17 08:00:53 +01:00
Xiang Xiao
69a6072946 arch/ceva: Replace adj_stack_ptr with stack_base_ptr
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
814cab1cd1 arch/ceva: Mark the allocated stack with TCB_FLAG_FREE_STACK
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
f8df491d5d arch/ceva: Update tls handle to the latest mainline
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
4bc5b246ac arch/ceva: Remove B2C and C2B
since TL420 doesn't support anymore, we
can safely remove the special hack for it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
YAMAMOTO Takashi
85af0f37ad arch/sim/src/Makefile: Fix build issues with clang on linux
This commit fixes at least two issues.

* Fix a build with clang on linux

```
/usr/bin/ld: cannot open linker script file nuttx.ld: No such file or directory
clang: error: linker command failed with exit code 1 (use -v to see invocation)
```

* Restore symbol renaming for clang on linux

I guess it actually depends on the linker.
For now, use CONFIG_HOST_MACOS.

This fixed the following crash seen with sim/linux built with clang.

```
    #135462 0x0000000000404a81 in nxtask_exithook (tcb=0x48f310 <g_idletcb>, status=1, nonblocking=0 '\000') at task/task_exithook.c:618
    #135463 0x0000000000402aed in exit (status=1) at task/exit.c:103
    #135464 0x0000000000475833 in host_abort (status=1) at sim/up_hostmisc.c:48
    #135465 0x000000000040e6c6 in up_assert (filename=0x47b167 "semaphore/sem_wait.c", lineno=113) at sim/up_assert.c:126
    #135466 0x000000000040850b in _assert (filename=0x47b167 "semaphore/sem_wait.c", linenum=113) at assert/lib_assert.c:36
    #135467 0x0000000000403a40 in nxsem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:113
    #135468 0x0000000000403b43 in sem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:271
    #135469 0x000000000040aad3 in lib_stream_semtake (list=0x7fca38b1c2d0) at stdio/lib_libstream.c:159
    #135470 0x000000000040a8e7 in lib_flushall (list=0x7fca38b1c2d0) at stdio/lib_libflushall.c:61
    #135471 0x0000000000404c3c in nxtask_flushstreams (tcb=0x48f310 <g_idletcb>) at task/task_exithook.c:520
    #135472 0x0000000000404a81 in nxtask_exithook (tcb=0x48f310 <g_idletcb>, status=1, nonblocking=0 '\000') at task/task_exithook.c:618
    #135473 0x0000000000402aed in exit (status=1) at task/exit.c:103
    #135474 0x0000000000475833 in host_abort (status=1) at sim/up_hostmisc.c:48
    #135475 0x000000000040e6c6 in up_assert (filename=0x47b167 "semaphore/sem_wait.c", lineno=113) at sim/up_assert.c:126
    #135476 0x000000000040850b in _assert (filename=0x47b167 "semaphore/sem_wait.c", linenum=113) at assert/lib_assert.c:36
    #135477 0x0000000000403a40 in nxsem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:113
    #135478 0x0000000000403b43 in sem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:271
    #135479 0x000000000040aad3 in lib_stream_semtake (list=0x7fca38b1c2d0) at stdio/lib_libstream.c:159
    #135480 0x000000000040a8e7 in lib_flushall (list=0x7fca38b1c2d0) at stdio/lib_libflushall.c:61
    #135481 0x0000000000404c3c in nxtask_flushstreams (tcb=0x48f310 <g_idletcb>) at task/task_exithook.c:520

```
2022-02-17 09:36:20 +08:00
YAMAMOTO Takashi
7fcfe40821 arch/sim/src/Makefile: Fix whitespace 2022-02-17 09:36:20 +08:00
Peter Kalbus
6abdf73535 sim: Initial support on MacOS M1 and Linux AARCH64 based hosts. 2022-02-17 09:35:09 +08:00
Xiang Xiao
1d963058b4 arch/sparc: Replace adj_stack_ptr with stack_base_ptr
since adj_stack_ptr doesn't exist anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-16 17:19:43 -03:00
Alan Rosenthal
8defb843aa Remove duplicate linker script definitions
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.

This PR cleans up the logic so they're only listed once.

 ## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!

 ## Testing
CI will test all build
2022-02-17 02:55:25 +08:00
Oki Minabe
68a305438b fix armv7-a gtm.h GTM_COMP1 and GTM_AUTO defines. 2022-02-16 18:50:42 +01:00
Oki Minabe
c1ea37742b fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
Simon Filgis
cf008c94cc arch/arm/samv7: fix peripheral id shift during transmit xdma configuration 2022-02-16 17:16:53 +01:00
Masayuki Ishikawa
b60b6120de arch: armv7-a: Fix arm_syscall for SYS_pthread_start
Summary:
- I noticed that pthread always crashes when started
  if CONFIG_BUILD_KERNEL=y
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-16 13:06:25 +01:00
Petro Karashchenko
41c95da594 register_driver: fix driver modes accross the code
State of problem:
 - Some drivers that do not support write operations (does not
   have write handler or ioctl do not perform any write actions)
   are registered with write permissions
 - Some drivers that do not support read operation (does not
   have read handler or ioctl do not perform any read actions)
   are registered with read permissions
 - Some drivers are registered with execute permissions

Solution:
 - Iterate code where register_driver() is used and change 'mode'
   parameter to reflect the actual read/write operations executed
   by a driver
 - Remove execute permissions from 'mode' parameter

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-02-16 16:15:29 +08:00
Xiang Xiao
db57e2cd8e Fix the minor style issue
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 15:26:38 +01:00
Masayuki Ishikawa
34cf6949ac arch: armv7-a: Add debug messages for addrenv
Summary:
- This commit adds debug messages for addrenv

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-15 17:22:52 +08:00
Masayuki Ishikawa
e7cb1b4fb1 arch: rt8920c: Move -fno-common option to ARCHCFLAGS/ARCHCXXFLAGS
Summary:
- Apply the same style as sabre-6quad

Impact:
- None

Testing:
- Build only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-15 16:27:53 +08:00
Xiang Xiao
6b02e32904 arch/sim: Remove 08 from the format string in up_vfork
to make the code more general for both x86 and x64.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 06:44:21 +01:00
Xiang Xiao
e1879e35cd arch/sim: Always typedef xcpt_reg_t to unsigned long
to simplify the code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 06:44:21 +01:00
Huang Qi
5cde8c6934 risc-v: Let g_cpu_basestack determined at compile time
Fix the CPU1 idle tasks stack corruption since the cpux's idle stack
is loaded from g_cpu_basestack (data section) before, but on this time
it maybe not ready since it is initialized by CPU0, and the value
from g_cpu_basestack is random.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-15 11:40:34 +09:00
Huang Qi
0d7f30c86d risc-v/k210: Move wfi to entry of the slave cpu boot routine
Fix another potential bug in non-smp case: load a value from overflowed address of g_cpu_basestack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-15 11:40:34 +09:00
fenghang
555d25633a add phyplus_rel_1.4
update source for phyplus driver rel_1.4

update source  for phyplus driver rel 1.4

update source for phyplus driver 1.4

update phy6222 config files
2022-02-15 10:21:10 +08:00
Xiang Xiao
4207882cdc arm/armv8-m: Handle the special irq correctly in up_secure_irq
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 09:45:34 +09:00
David Sidrane
1ca952243c stm32h7:flash can not use usleep
commit 328374f4658d11655f268f968f4c6c7a3942f320

   changed the wait to use usleep. This killed the
   write performace from the published values in the
   datasheet of ~100 us to 2 mS per 256 bits. On
   a 1000 per tick config. It can be 10 X worse
   on the default 100 per tick config.

   This changes uses up_udelay.
2022-02-15 02:09:04 +08:00
David Sidrane
8659a31c9d stm32h7:flash Fix lock violations 2022-02-15 02:09:04 +08:00
David Sidrane
8ca4cf49b1 stm32h7:Fix build for all config {R|T}XDMA states 2022-02-14 18:43:30 +01:00
Xiang Xiao
17a7d612df arch: Replace nx_vsyslog with vsyslog
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-14 09:41:45 -03:00
chao.an
4be416a2a8 arm/backtrace: fix the compile warning
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-14 16:29:38 +08:00
Huang Qi
b8477f857b k210: Use common cpu idle stack implementation
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
Huang Qi
55d88627a0 risc-v: Implement common up_cpu_idlestack
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
raiden00pl
00917bfe9d stm32/fdcan: add CAN FD frames support 2022-02-14 10:42:01 +08:00
raiden00pl
dd8408a973 stm32/fdcan: use array indexes when accessing RX/TX FIFO 2022-02-14 10:42:01 +08:00
Michael Jung
70dae3bb3b Add arm_tcbinfo.c to stm32u5's common C sources
And re-order the list of common C sources alphabetically.

Signed-off-by: Michael Jung <mijung@gmx.net>
2022-02-13 16:32:35 +08:00
Michael Jung
5c1c939cdc stm32u5: Architecture Support for STM32U5
Architecture support for STMicroelectronics STMU585xx MCUs.  This is
based on corresponding code for STM32L5, but has been considerably
adjusted.  Tested with a B-U585I-IOT02A board and a simple NSH
configuration, but only running NuttX in the non-secure world with
TrustedFirmware-M.

Signed-off-by: Michael Jung <mijung@gmx.net>
2022-02-13 16:32:35 +08:00
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-13 14:37:57 +08:00
Michal Lenc
56b3fc0ef9 arch/arm/src/samv7: added support for PWM driver
This commit adds initial support for PWM driver to SAM MCU series.
Only general PWM on PWMH output is currently supported, complementary
output on PWML is not allowed. The current state of the driver also does
not support external triggering of other perihperals.

Multichannel option is supported. The functionality of the driver was
tested on an example pwm application and with a real time control system.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-02-13 03:20:07 +08:00
Huang Qi
95b0c85f58 arch: Add xxx_tcbinfo.c to SoC level Make.defs
Fix build break with CONFIG_DEBUG_TCBINFO enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-12 21:07:35 +09:00
Peter Kalbus
271518a5ff sim: detect clang native compiler on MacOS. 2022-02-11 21:23:07 +08:00
Huang Qi
3fe9c9523c risc-v: Fix style issue in SoC's Make.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-11 15:20:17 +08:00
Alan C. Assis
d49ad207ef esp32c3: Fix issue #5377 UART1 not working because clock as disabled 2022-02-11 10:01:25 +08:00
zhuyanlin
c833048484 xtensa:kconfig: move ARCH_HAVE_TESTSET config to chip
Some xtensa arch have not implentment testset instructions

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-10 14:22:58 +08:00
Huang Qi
7134220ae2 risc-v: Remove duplicated up_idle logic
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
9223547afc risc-v: Support cpu activity led in up_idle
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
6f18747dc2 risc-v: Add WFI to up_idle and fix compile issue
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
zhuyanlin
3ab65f9b08 armv7-a/r: use flush/clean_all if size large than cache size
For cache flush/clean performance

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-09 18:16:31 +01:00
zhuyanlin
4eba2f3527 armv7-a/r:cache: add cp15_cache_size function
Add cp15_cache_size function for armv7-a/r

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-09 18:16:31 +01:00
Huang Qi
9d91d69ee0 arch/risc-v/mpfs: Remove riscv_pthread_exit.c in Make.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit"
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Alin Jerpelea
0cfdfde6c7 arch: sim: update licenses for FishSemi
FishSemi is part of Xiaomi and according to xiaoxiang781216
the SGA covers those files

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
Alin Jerpelea
7a674b6287 Makefiles: change license to Apache
Make files are recipes based on contributions from from Gregory Nutt

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
Alin Jerpelea
e2725d536a arch: sim: update licenses to Apache
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
zhuyanlin
cc8ab23550 armv7-r/a: fix a4 register use in xxx_invalidate/flush/clean_all.S
Use sub loop instead of add loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-08 19:39:43 +09:00
SPRESENSE
8de07b2ae8 boards: cxd56xx: audio: Support I2S input
Enable the driver setting of I2S input.
2022-02-08 10:47:03 +01:00
Xiang Xiao
963feca4a1 arch/sim: Don't add up_tls_size in up_use_stack before foward to up_create_stack
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-07 08:45:34 +01:00