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aa1708e7c0
Commit Graph

10485 Commits

Author SHA1 Message Date
Gregory Nutt
aa1708e7c0 6LoWPAN: Update README; fix duplicate and bad memcpy in loopback driver. 2017-06-26 10:53:57 -06:00
raiden00pl
715d6fa9ff stm32f33xxx_rcc: cleanup + move hrtim clock source selection 2017-06-26 18:30:10 +02:00
raiden00pl
aead2b2afd stm32f33xxx_rcc.h: fix typo 2017-06-26 18:26:59 +02:00
Juha Niskanen
56eeb40958 STM32L4 serial: Allow configuring Rx DMA buffer size 2017-06-26 09:19:42 -06:00
Juha Niskanen
90ccdf287d STM32 L4 DMA: Correct USART3_RX bad channel definition 2017-06-21 08:40:33 -06:00
David Sidrane
345ea957cf Merged in david_s5/nuttx/upstream_kinetis (pull request #414) 
Kinetis:I2C fixed mis-placed kinetis_i2c_endwait

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-20 20:22:17 +00:00
David Sidrane
839a6e09f4 Kinetis:I2C fixed mis-placed kinetis_i2c_endwait 
Fixed accedently replaced post with wait.
 2017-06-20 10:01:35 -10:00
Gregory Nutt
5de74441a6 Costmetic change from review of last PR 2017-06-20 13:33:14 -06:00
David Sidrane
1ee03d7500 Merged in david_s5/nuttx/upstream_kinetis (pull request #413) 
Kinetis:I2C driver added I2C3, reference counting and reset

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-20 19:31:38 +00:00
David Sidrane
9e0f583774 Kinetis:I2C driver added I2C3, reference counting and reset 
Refactored the driver to support reference counting and reset
   added I2C3
 2017-06-20 08:34:12 -10:00
Sebastien Lorquet
0bf4893b2c STM32: Allow clock frequencies > 168 Mhz on stm32f427/429. We need to enable the power overdrive for this case. This patch allows the required bits to be set in proper sequence. It also modifies the local register access operations to allow more than 16-bit registers. 2017-06-20 11:56:54 -06:00
Juha Niskanen
326ab01a91 STM32 F7: Set I2C4 SDA and SCL pins to open drain mode 2017-06-20 08:06:30 -06:00
Juha Niskanen
2c548a4e58 STM32 L4: I2C4 was writing to wrong RCC registers 2017-06-20 08:04:09 -06:00
Gregory Nutt
47ad81b3e5 Trivial spelling fix 2017-06-20 08:02:42 -06:00
Pekka Ervasti
2eb782961f STM32 L4: Set I2C SDA and SCL pins to open drain mode. 2017-06-20 07:59:27 -06:00
Jussi Kivilinna
a1ee9547f3 stm32_adc: invalidate dma buffer before use. Missing invalidation caused old samples being fetched from cache. 2017-06-19 07:52:19 -06:00
raiden00pl
c29c4e2ec2 stm32_hrtim: remove unneeded definitions 2017-06-18 18:08:25 +02:00
raiden00pl
4e0f45f252 stm32_hrtim: fix initialization bug, minor changes 2017-06-18 18:06:37 +02:00
raiden00pl
cd30545cd9 stm32_hrtim: ADC triggering and DAC synch events 2017-06-18 15:26:39 +02:00
raiden00pl
96e639262a stm32_hrtim: add hrtim ops 2017-06-18 11:01:36 +02:00
raiden00pl
797e286cb0 stm32_hrtim: timers mode configuration 2017-06-18 09:28:05 +02:00
raiden00pl
dfeffefa69 stm32_hrtim: typo 2017-06-18 08:02:15 +02:00
Gregory Nutt
0024840f7d Trivial, cosmetic changes from review of last PR 2017-06-17 14:44:11 -06:00
raiden00pl
b48a86ee33 Merge remote-tracking branch 'upstream/master' 2017-06-17 22:18:03 +02:00
raiden00pl
4d9d3c4a9c stm32_hrtim: cosmetics 2017-06-17 22:12:56 +02:00
raiden00pl
5e3360b8b9 stm32_hrtim: faults and events configuration 2017-06-17 21:56:11 +02:00
David Sidrane
c79d4d1988 stm32:flash add CONFIG_STM32_STM32F469 to list defining OPTCR1 2017-06-16 14:16:32 -10:00
Gregory Nutt
5245cbc6f5 STM32 SPI/I2S: Back out a bad pin mapping change from 4ab2a3661e. Try to staighten out some I2C3 and SPI3 pin configuration stuff. 2017-06-16 09:34:22 -06:00
Sebastien Lorquet
4d9be9bc20 STM32 F4 FLASH: Enable/disable the flash write protection on any sector. I have verified it to work on the stm32f427. 2017-06-16 08:46:57 -06:00
raiden00pl
bd7bee5db0 stm32_hrtim: structures for deadtime and chopper, cosmetics 2017-06-16 11:36:23 +02:00
David Sidrane
64e3dc5e8b Merged in david_s5/nuttx/upstream_samv7_twi (pull request #399) 
samv7:twihs driver add reference counting

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-15 21:45:07 +00:00
David Sidrane
d9d32ac808 samv7:twihs driver add reference counting 2017-06-15 11:16:28 -10:00
raiden00pl
268c6d0b7d stm32_hrtim: outputs enable, period and compare functions, cosmetics 2017-06-15 16:45:21 +02:00
Gregory Nutt
d958cec7a4 Cosmetic changes from review of last PR 2017-06-15 06:58:55 -06:00
Hidetaka
0f1d388248 Merged in TJ-Hidetaka-Takano/nuttx-pr/feature/fix-kconfig (pull request #394) 
Fixed typo "CORTEXR5F" in arch/arm/Kconfig

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-15 12:12:31 +00:00
Hidetaka
9dfa8f7df9 Merged in TJ-Hidetaka-Takano/nuttx-pr/feature/fix-armv7m-toolchain-def (pull request #395) 
Fixed ARMv7-M Toolchain definition for Cortex-M4.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-15 12:12:01 +00:00
Hidetaka Takano
5591fc6b16 Fixed ARMv7-M Toolchain setting. 
- Cortex-M4 only have Single Precision FPU.
 2017-06-15 20:52:37 +09:00
Hidetaka Takano
d665392873 Fixed typo "CORTEXR5F" in arch/arm/Kconfig 2017-06-15 20:44:06 +09:00
raiden00pl
96d40dec40 stm32_hrtim: cosmetic 2017-06-15 11:20:40 +02:00
Leif Jakob
4a79547fb8 multiple fixes for stm32f1xx RTC clock 
- compile issues because of missing RTC_MAGIC #defines
- missing functionality based on RTC_MAGIC in RTC based on stm32_rtcounter.c
- IRQ setup from up_rtc_initialize was later reset in up_irqinitialize
- write access to backup registers without enabling access to backup domain
- possible races in set/cancel alarm
tested with STM32F103C8 only
device now wakes up from forced STANDBY mode by alarm
 2017-06-14 22:36:40 +02:00
David Sidrane
b2d929e40a Kinetis:SPI driver 2017-06-13 17:46:57 -10:00
David Sidrane
de3695d32b kinetis:lpserial fixed header inclusion 2017-06-13 17:46:56 -10:00
Gregory Nutt
e379491d13 STM32/STM32L4: Review of last commit -- Eliminate possible underflow 2017-06-13 07:05:46 -06:00
JM
7903a8a46c stm32/stm32l4 PWM: While attempting to output a 70 MHz square wave from the timer output of a STM32 clocked at 140 MHz (which works fine in baremetal C), I stumbled on what I believe to be an error in arch/arm/src/stm32/stm32_pwm.c. Line 1304 we are told that 
reload = timclk / info->frequency;

which I belive to be incorrect, it should be

reload = timclk / info->frequency - 1;

since starting to count from 0, if I want to output half of the TIM clock, I must count to 1 and not to 2.

Surely enough, the original code did output 140/3=47 MHz, while this correction does allow the output up to 70 MHz.

I am not sure this affects most users generating slow PWM (e.g. PX4) but for frequencies
close to the PCLK, indeed the difference becomes significant.
 2017-06-13 06:01:13 -06:00
raiden00pl
f6ba4642a3 stm32_hrtim: GPIOs configuration + EEV and FAULT strucutres 2017-06-12 18:45:58 +02:00
Gregory Nutt
f5f1c73b54 Based on the last PR, review all serial driver vector attachment. Found one additional error and updated all relevant drivers to current interrupt parameter passing. 2017-06-12 06:22:35 -06:00
Masayuki Ishikawa
93a2d52b56 i.MX6: Fix a wrong parameter passed when calling irq_attach() in imx_serial.c 2017-06-12 13:34:53 +09:00
raiden00pl
de8cd6c870 stm32_hrtim: add character driver 2017-06-11 20:51:23 +02:00
Gregory Nutt
fe813545e8 STM32F33: Forgot to add new files that were a part of the last patch before committing. 2017-06-11 11:00:29 -06:00
Mateusz Szafoni
437ad3ccb2 STM32F33: Fix hrtim definitions, Add beginning of HRTIM driver 2017-06-11 10:49:20 -06:00