Gregory Nutt
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39183d37b8
|
Change all time conversions. Yech. New timer units in microseconds breaks all existing logic that used milliseconds in the conversions. Something likely got broken doing this, probably because I confused a MSEC2TICK conversion with a TICK2MSEC conversion. Also, the tickless OS no appears fully functional and passes the OS test on the simulator with no errors
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2014-08-07 18:00:38 -06:00 |
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Gregory Nutt
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594083d870
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Rename up_timerinit() to up_timer_initailize(); Add prototypes for candidate interfaces for the tickless OS; Don't build existing timer initialization logic if CONFIG_SCHED_TICKLESS is defined.
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2014-08-06 16:26:01 -06:00 |
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Gregory Nutt
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d4a29fcf7e
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SAMA5D3 HSMCI: TX DMA is again disabled
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2014-08-05 07:07:39 -06:00 |
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Gregory Nutt
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553a16fac5
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SAMA5 PCK: Add Main clock as an option for the PCK clock source
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2014-08-03 10:17:50 -06:00 |
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Gregory Nutt
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1fc8f2b06d
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SAMA5 SSC: Verify that the requested bit width is supported. Correct some alignment tests that depend upon the data bit width.
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2014-08-02 14:26:49 -06:00 |
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Gregory Nutt
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715cf207ea
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SAMA5 WM8904: Fix errors in programmable clock output configuration
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2014-08-01 15:18:58 -06:00 |
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Gregory Nutt
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5e92347d60
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SAMA5 SSC: Start Delay is now configurable
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2014-08-01 14:10:37 -06:00 |
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Gregory Nutt
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d68a6059e0
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SAMA5 SSC: Frame Synch Delay is now configurable
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2014-08-01 12:25:31 -06:00 |
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Gregory Nutt
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c2c2921901
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SAMA5D SSC: Needs to account for data offset in audio buffer.
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2014-07-31 19:14:24 -06:00 |
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Gregory Nutt
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513329fd24
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SAMA5D3X-EK: Add support for the WM8904 audio CODEC
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2014-07-31 11:14:57 -06:00 |
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Gregory Nutt
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ffcc0b8da3
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SAMA5: Changes needed for a clean SAMA5D3 build after all of the recent SAMA5D4 changes.
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2014-07-31 11:09:56 -06:00 |
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Gregory Nutt
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c0c4cda763
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SAMA5 HSMCI: e-enable TX DMA and verify that DMA writes to the SD card are functional. They are so now TX DMA is re-enabled in the driver. This might affect the SAMA5D3 platforms where the TX DMA problem was found. The SAMA4D3 and 4 use the same HSMCI driver. Much has change since then and it is not surprising that DMA is now functional. However, the has not be re-verified on the SAMA5D3 which has a different DMA controller.
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2014-07-30 11:20:06 -06:00 |
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Gregory Nutt
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611ea42dbf
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SAMA5D HSMCI: Fix a problem on card insertion/removal callback handling. Interrupts were being disable so that the callbacks occurred with interrupts disabled. This resulted in loss of some interrupts and some not-so-good behaviors. The solution is to perform all callbacks on the work thread unconditionally (2014-7-29).
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2014-07-30 10:19:41 -06:00 |
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Gregory Nutt
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059812c872
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SAMA5D HSMCI: Add method to do RX transfer without DMA. The 8-byte SCR transfer was failing silently with the DMA transfer, leaving the SD card in single bit mode
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2014-07-29 21:13:28 -06:00 |
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Gregory Nutt
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e053158f95
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SAMA5D-EK: Correct system timer frequency. Input clock is MCK/2, not MCK
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2014-07-29 07:12:36 -06:00 |
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Gregory Nutt
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29ea8ab0e4
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Cosmetic changes to comments
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2014-07-29 07:11:16 -06:00 |
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Gregory Nutt
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42a975af74
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Fixes to last SAMA5 PMIC checkin
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2014-07-28 17:09:37 -06:00 |
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Gregory Nutt
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dd4be66f1c
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ARM: Move L2 cache initialization to much later in the sequence
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2014-07-27 10:03:33 -06:00 |
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Gregory Nutt
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ee59870325
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Enables cache early in boot-up sequence
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2014-07-26 18:48:00 -06:00 |
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Gregory Nutt
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4e146d2ec2
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Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled
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2014-07-26 18:47:33 -06:00 |
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Gregory Nutt
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6d9ca195ee
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arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache.
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2014-07-26 16:50:08 -06:00 |
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Gregory Nutt
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e74f37445b
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rch/arm/armv7-a/l2cc_pl310.h: Move arch/arm/sama5/chip/sam_l2cc.h to arch/arm/armv7-a/l2cc_pl310.h. Adjust the two corresponding Kconfig files as well.
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2014-07-25 17:25:17 -06:00 |
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Gregory Nutt
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949e002d76
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Fix a recently introduced typo that was being masked by some bad conditional compilation
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2014-07-22 11:45:14 -06:00 |
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Gregory Nutt
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af8f5f4bdc
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SAMA5D4 XDMAC: Never sets a channel as secure. Will probably have to revisit this
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2014-07-21 17:46:35 -06:00 |
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Gregory Nutt
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4ce2e094ba
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SAMA5D4: Fix some HSMCI issues when XDMAC0 is enabled
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2014-07-21 17:45:48 -06:00 |
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Gregory Nutt
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80c0b5628d
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SAMA5 HSMCI: Correct multi-block DMA setup; Fixes related to DMA timeout. Still problems with HSMCI DMA via XDMAC
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2014-07-21 16:49:56 -06:00 |
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Gregory Nutt
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519c8f3e97
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SAMA5 XDMAC: Missing some CUBC bits
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2014-07-21 16:47:16 -06:00 |
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Gregory Nutt
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2d69c2f519
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SAMA4D5 HSMCI: Set burst size to 1, sample DMA registers on timeout, and don't return from transfer until BOTH the HSMCI transfer and DMA complete
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2014-07-21 13:24:55 -06:00 |
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Gregory Nutt
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c5b58b189c
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XDMAC register sampling missed CIM register; Should not set SWREQ bit in DMA setup
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2014-07-21 13:23:36 -06:00 |
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Gregory Nutt
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35ea8f1542
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Fix a commented out assertion
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2014-07-20 17:06:55 -06:00 |
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Gregory Nutt
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b207138be9
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Fix typos in comments
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2014-07-20 13:09:47 -06:00 |
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Gregory Nutt
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7ba2d9ed36
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SAMA5D4-EK: PIO Schmitt trigger logic backward
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2014-07-20 13:04:30 -06:00 |
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Gregory Nutt
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9392953ea1
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WM8904 w/NxPlayer: Fix some compile errors and warnings with debug enabled
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2014-07-20 09:17:36 -06:00 |
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Gregory Nutt
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7c56185006
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SAMA5D ADC: Fix some typos in conditional compilation
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2014-07-19 13:56:48 -06:00 |
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Gregory Nutt
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3c29703c42
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SAMA5 SCK: The SAMA5D3 does things a little differently
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2014-07-19 13:55:53 -06:00 |
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Gregory Nutt
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e82143ac38
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SAMA5 PCK: Add support for the slow clock as the PCK clock source
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2014-07-19 13:55:08 -06:00 |
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Gregory Nutt
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8986bd3976
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SAMA5: Update slow clock logic. Things work a little differently on the SAMA5D3
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2014-07-19 13:25:59 -06:00 |
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Gregory Nutt
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813eade679
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SAMA5: Add slow clock support
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2014-07-19 13:07:55 -06:00 |
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Gregory Nutt
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c7055a4cb8
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SAMA5D4-EK: Add WM8904 initialization logic
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2014-07-19 11:58:53 -06:00 |
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Gregory Nutt
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8055a59d49
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SAMA5 LCDC: Back out the delay kludge. Increase the LCDC input clock from MCK to 2*MCK was sufficient for all timing instbility problems
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2014-07-12 11:24:14 -06:00 |
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Gregory Nutt
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424d47cfee
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SAMA5D4-EK LCDC: Change source clock to 2*Mck seems to solve stability issues
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2014-07-12 09:45:05 -06:00 |
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Gregory Nutt
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30603b1021
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SAMA5D4-EK LCDC: Adding a delay after enabling the LCD solves lots of start-up timing issues
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2014-07-12 08:05:22 -06:00 |
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Gregory Nutt
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67468408ae
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SAMA5D4-EK LCD: Actual hardware with appears to be RGB888
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2014-07-10 12:23:41 -06:00 |
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Gregory Nutt
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c7d53cb927
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SAMA5D4-EK: LCDC works (with a few color problems)
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2014-07-10 12:03:10 -06:00 |
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Gregory Nutt
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6563ae07c2
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Don't have to set SDA high initially in I2C reset because that is done by the pin configuration
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2014-07-09 17:17:32 -06:00 |
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Gregory Nutt
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fc973eb512
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SAMA5 PIO: Fix a typo in Schmitt trigger configuration; Configure pin as a a vanilla input first so that final pin configuration is more read-able (i.e., easier to debug)
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2014-07-09 17:16:43 -06:00 |
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Gregory Nutt
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0d4255257d
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SAMA5 I2C Reset: More changes... still does not work right
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2014-07-09 15:09:06 -06:00 |
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Gregory Nutt
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c1ca11331d
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SAMA5 TWI: Some restructured needed by up_i2creset. Also timeout needs to vary with the size of the transfer and if debug is on or not
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2014-07-09 13:39:10 -06:00 |
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Gregory Nutt
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ee351dc695
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Use sam_pio_forceclk() so that we can read the current state of an open-drain output in the TWI reset logic.
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2014-07-09 11:31:21 -06:00 |
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Gregory Nutt
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c4b9eaa01f
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Add a new interface sam_pio_forceclk() that can be used to force PIO clocking on. I am afraid I was too conservative with PIO clocking in the initial design; this is the price
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2014-07-09 11:26:07 -06:00 |
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Gregory Nutt
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6c4f57b0dc
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SAMA5 TWI: Add support for up_i2creset
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2014-07-09 09:51:28 -06:00 |
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Gregory Nutt
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446d9daa94
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SAMA5D4 LCDC: Adapt the SAMA5D3 LCDC driver to work with the SAMA5D4 which has no hardware cursor
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2014-07-08 12:45:16 -06:00 |
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Gregory Nutt
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8bc8a86b90
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SAMA5D3/4 HEAP: Add a configuration option to reserve DRAM for a framebuffer when executing out of DRAM.
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2014-07-08 12:43:38 -06:00 |
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Gregory Nutt
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3fe95f83de
|
Fix some cloned errors in SAM GPIO interrupt setup
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2014-07-07 15:54:37 -06:00 |
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Gregory Nutt
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14c90921b3
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SAMA5D3/4: Fix two issues associated with PIO interrupts
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2014-07-07 14:16:29 -06:00 |
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Gregory Nutt
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ae95f4e4d2
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SAMA5D3/4 I2C: Test for read or write operation was reversed. How could this have worked before?
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2014-07-07 09:54:43 -06:00 |
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Gregory Nutt
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56629f7fde
|
maXTouch: Fix test of I2C_TRANSFER return value
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2014-07-06 08:51:38 -06:00 |
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Gregory Nutt
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d7fe256821
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NET: emoved all includes of uip.h; added includes of ip.h wherever needed. Tried to fix problems of the now missing sneak inclusions because uip.h was removed. There are probably a few of these that were missed.
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2014-07-04 19:13:08 -06:00 |
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Gregory Nutt
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99ce3a44d7
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Remove all inclusion of uip.h
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2014-07-04 16:58:22 -06:00 |
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Gregory Nutt
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11e3a21411
|
NET: More renaming
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2014-07-04 15:40:49 -06:00 |
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Gregory Nutt
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77439f3c75
|
AMA5 OHCI: Pointers to allocated port values were not being nullified after being deallocated. This caused some assertions when debug was enabled
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2014-07-04 08:17:14 -06:00 |
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Gregory Nutt
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2bd5963622
|
SAMA5 OHCI: Fix an error in a DEBUGASSERT statement. Caused assertion to fire inappropriately when a low- or full-speed device is removed and CONFIG_DEBUG=y
|
2014-07-03 13:06:28 -06:00 |
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Gregory Nutt
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8b2fb4725b
|
SAMA5D3/4: UPLL divisor to generate 48MHz for OHCI is different from the two families. No idea why.
|
2014-07-03 12:28:11 -06:00 |
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Gregory Nutt
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fb44a97359
|
SAM Ethernet: Eliminate a warning
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2014-07-02 17:35:41 -06:00 |
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Gregory Nutt
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596dbc20ef
|
SAMA5D4-EK: NSH should run at 528MHz
|
2014-07-02 15:31:52 -06:00 |
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Gregory Nutt
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30fc821bc8
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SAMA5D4-EK: NSH configuration now has TWI0 enabled and supports the I2C tool
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2014-07-02 13:51:57 -06:00 |
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Gregory Nutt
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a420171a4a
|
SAMA5D4 EMAC: Add a kludge to work around a suspected hardware issue
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2014-07-02 12:17:01 -06:00 |
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Gregory Nutt
|
e7aa949380
|
SAM3/4 and SAMA5 Ethernet: Fix an error in the function that determines the number of free TX descriptors
|
2014-07-02 10:40:11 -06:00 |
|
Gregory Nutt
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f5abca3952
|
SAMA54D-EK: Don't disable any features in the NSH configuration. Comments updated in several files
|
2014-07-02 08:54:53 -06:00 |
|
Gregory Nutt
|
313982ba18
|
NET: Rename XYZ_uiptxpoll to just XYZ_txpoll
|
2014-07-01 18:41:08 -06:00 |
|
Gregory Nutt
|
a2507acab8
|
SAMA5D4: Add a configuration option to force EMAC driver debug
|
2014-07-01 18:00:39 -06:00 |
|
Gregory Nutt
|
289dc6dc71
|
SAMA5D4: Fix error in EMAC driver (plus related EMAC/GMAC drivers)
|
2014-07-01 11:22:19 -06:00 |
|
Gregory Nutt
|
621ec21bfd
|
Rename uip_poll->devif_poll and uip_timer->devif_timer
|
2014-06-30 18:40:41 -06:00 |
|
Gregory Nutt
|
ade8807a61
|
Rename uip_input to devif_input
|
2014-06-30 18:11:17 -06:00 |
|
Gregory Nutt
|
c5f2ec1637
|
Fix typo/compile error introduced with last HSMCI changes
|
2014-06-30 16:08:29 -06:00 |
|
Gregory Nutt
|
d8f4b29d5f
|
SAM3/4: Important bugfix. Values read from PIO input pins do not change unless clocking to the PIO block is enabled
|
2014-06-30 14:26:09 -06:00 |
|
Gregory Nutt
|
03f3f8966c
|
SAMA5D3/4: Fix some logic in conversion of physical and virtal DRAM addresses when running out of DRAM
|
2014-06-30 11:04:34 -06:00 |
|
Gregory Nutt
|
f6a3d4b728
|
SAMA5D4: Don't touch ISLR unless PIO is configured as an interrupt
|
2014-06-30 09:17:42 -06:00 |
|
Gregory Nutt
|
c4ace8244d
|
Fix typos in debug statements
|
2014-06-30 07:38:02 -06:00 |
|
Gregory Nutt
|
ce710bb94a
|
SAMA5 PIO: Add support for secure interrupts; Fix PIO debug output
|
2014-06-29 17:46:55 -06:00 |
|
Gregory Nutt
|
e681a582a7
|
SAMA5: Remove kruft in PIO header file
|
2014-06-29 17:45:42 -06:00 |
|
Gregory Nutt
|
70fa9ad81d
|
SAMA5D4 HSMCI: Fix a compiler in a debug statement
|
2014-06-29 12:01:08 -06:00 |
|
Gregory Nutt
|
1384148415
|
SAMA5D4 XDMA: Fix some typos
|
2014-06-29 11:24:57 -06:00 |
|
Gregory Nutt
|
9fab30e3b5
|
Fix system bus IDs for SAMA5D4; Don't use explicit PERIPHID_SHIFT for symmetry with memory
|
2014-06-29 11:24:10 -06:00 |
|
Gregory Nutt
|
d4f27b9e08
|
SAMA5D: Don't use explicit DMACH_FLAG_MEMPID_SHIFT; it does not exist in the SAMA5D4
|
2014-06-29 09:52:07 -06:00 |
|
Gregory Nutt
|
7c8c583722
|
SAMA5: Add configuration to assign an XDMAC channel to an HSMCI
|
2014-06-29 08:43:46 -06:00 |
|
Gregory Nutt
|
b7fad79a1d
|
SAMA5D4-EK: Updates to get the at25boot configuration building correctly
|
2014-06-28 09:39:50 -06:00 |
|
Gregory Nutt
|
e4990dda4d
|
Rename uip_driver_s net_driver_s
|
2014-06-27 16:48:12 -06:00 |
|
Gregory Nutt
|
6a451baa51
|
SAMA5D4: Add configuration to redirect all interrupts to the AIC
|
2014-06-26 11:51:39 -06:00 |
|
Gregory Nutt
|
57383ea2f3
|
Rename ip_eth_hdr to eth_hdr_s
|
2014-06-25 09:57:52 -06:00 |
|
Gregory Nutt
|
11896e1481
|
Move the remaining files from include/nuttx/net/uip to include/nuttx/net; Rename *_internal.h header files in net/ to just *.h
|
2014-06-24 10:14:15 -06:00 |
|
Gregory Nutt
|
b34a1f1e01
|
Move include/nuttx/net/uip/uip-arch.h to include/nuttx/net/netdev.h
|
2014-06-24 09:28:44 -06:00 |
|
Gregory Nutt
|
4e3c794363
|
SAMA5D4: Add missing mappings for the VDEC and L2CC memory regions
|
2014-06-21 14:25:47 -06:00 |
|
Gregory Nutt
|
4b9666658e
|
Correct type of SAMA5 arm_decodefiq() return value
|
2014-06-21 10:34:35 -06:00 |
|
Gregory Nutt
|
0a134f0158
|
Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handling
|
2014-06-21 09:55:09 -06:00 |
|
Gregory Nutt
|
c68d2532be
|
SAMA5D4: Add support for secure/FIQ interrupts; SAIC supports need to be be enabled unconditionally
|
2014-06-20 18:16:41 -06:00 |
|
Gregory Nutt
|
8f4f73884b
|
SAMA5D4: Fix MATRIX32 base address
|
2014-06-20 18:15:13 -06:00 |
|
Gregory Nutt
|
8fb8774c26
|
SAMA5D4: Minor fixes to get working with SAMA5D3 again
|
2014-06-20 16:01:45 -06:00 |
|
Gregory Nutt
|
0a2133b57f
|
SAMA5D4: Add partial support for secure interrupt controller (SAIC)
|
2014-06-20 15:22:00 -06:00 |
|
Gregory Nutt
|
aecddf9b52
|
SAMA5D4: USART peripheral clock appears to be MCK/2
|
2014-06-20 11:40:36 -06:00 |
|