Commit Graph

1691 Commits

Author SHA1 Message Date
Eren Terzioglu
99ea8b7832 esp32[c3|c6|h2]: Add gspi master support 2024-06-12 23:35:24 +08:00
Tiago Medicci Serrano
6c3eeb7d5c espressif: Remove outdated config about IDF bootloader
For newer devices, IDF bootloader is not supported because the
devices are able to boot directly into NuttX or use MCUBoot to
enable OTA and security features.
2024-06-12 16:11:56 +08:00
Tiago Medicci Serrano
480ad6b631 esp: Make the legacy bootloader (IDF bootloader) option visible
This commit enables users to select the legacy bootloader (IDF
bootloader) in `menuconfig` directly. Please note, that this is a
legacy option intended to support devices already deployed and it
isn't recommended for new designs.
2024-06-12 16:11:56 +08:00
Matheus Catarino
c6eea4ad8b add LDC2 (dlang) support
*Note:* ldmd2 is ldc2-wrapper, allow using dmd frontend flags.
      This support may be extended to gdc (gnu) if nuttx developers demand it
  or are interested in it.
2024-06-06 09:32:56 +08:00
Jani Paalijarvi
b32a1dfd3d risc-v/mpfs: Add error handling for PMP conf
Check return value of mpfs_board_pmp_setup() and
jump to mpfs_board_pmp_error() in case of error.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-06-05 12:07:02 -03:00
Eren Terzioglu
24af23e49c esp32[c3]: Add XTWDT support 2024-06-04 17:42:07 -03:00
Stuart Ianna
e3056c781e arch/risc-v/riscv_mtimer: Update the mtimecmp value once per interrupt event.
Cache the next timeout value in the drivers instance and update the mtimecmp value once. This is advantageous as the opensbi ecall to set the timer is expensive in systems which don't have the supervisor mode timer extension.
2024-06-02 09:28:19 -03:00
Ville Juven
e6973c764c riscv/syscall: Optimize user service call performance
This patch changes how user service calls are executed:
Instead of using the common interrupt logic, execute the user service
call directly.

Why? When a user makes a service call request, all of the service call
parameters are already loaded into the correct registers, thus it makes
no sense to first clobber them and then reload them, which is what the
old logic does. It is much more effective to run the system call directly.

During a user system call the interrupts must be re-enabled, which the
new logic does as soon as we know the exception is a user service call
request.

This patch does NOT change the behavior of reserved system calls (like
switch_context), only the user service call request is affected.
2024-06-01 10:40:53 -03:00
Ville Juven
a5574d9485 risc-v_percpu: Add TCB to the per CPU structure
Also, convert the type to union; we don't need the list element once
the item has been popped from the free list (the linkage is never needed
when the item is in use).
2024-06-01 10:40:53 -03:00
Ville Juven
6bad48e4c7 riscv_syscall.S: Remove duplicated code
Return from exception is common code for both system calls and
exceptions
2024-06-01 10:40:53 -03:00
Stuart Ianna
1f02c05c6d arch/litex/litex_arch_alarm: Support tickless schedular with arch alarm.
This provides an alternate tickless scheduling method, which uses the riscv
mtimer as a timebase, allowing the time and timeh registers to used
throughout an application.

The exiting tickless method, using Litex's timer0 has been left in place, as
it is a more performant option, but currently has the potential issue
identified in #11189.
2024-05-31 10:21:44 +08:00
Ville Juven
c1f3245167 riscv-v/fork.S: Fix clobbering of s0 in fork()
Value of s0 (callee-saved) must be preserved through the call, use
a0 (caller-saved) to calculate the original SP instead.
2024-05-31 02:29:48 +08:00
xuxin19
275ec7102c cmake:bugfix CMake compilation options settings should not use strings
when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-05-30 10:02:10 -03:00
Jani Paalijarvi
cfa544357e mpfs_mpu: Check that size is valid for MPUCFG
The size must be power-of-two for NAPOT according to the the PMP spec.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-24 21:32:55 +08:00
Jani Paalijarvi
9d4bd915eb riscv_pmp.c: Check that size is power of two for NAPOT
The size must be power-of-two according to the the PMP spec.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-24 21:32:55 +08:00
Eren Terzioglu
ea9eea4096 esp32[c3|c6|h2]: Add MWDT1 support 2024-05-24 13:59:03 +08:00
Eren Terzioglu
aa0bb55529 esp32[c3|c6|h2]: Add RWDT support 2024-05-24 13:59:03 +08:00
Eren Terzioglu
44e118eaf2 esp32[c3]: Add RTC IRQ support 2024-05-24 13:59:03 +08:00
Yanfeng Liu
f8749ef0e0 arch/risc-v: guard tcb->name usage
Add guard for tcb->name field usage as it is not always available.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-22 19:06:07 +08:00
Yanfeng Liu
7db71c8ee4 ci/riscv: fix unused var in esp_twai.c
This is to fix issue in [this log](https://github.com/apache/nuttx/actions/runs/9173629303/job/25222879619):

```
Configuration/Tool: esp32c3-generic/twai esp32c6-devkitm/twai esp32c6-devkitc/twai  esp32h2-devkit/twai
Error: common/espressif/esp_twai.c:242:7: error: variable 'ret' set but not used [-Werror=unused-but-set-variable]
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-22 16:40:13 +08:00
yinshengkai
20ebe0e64c Replace all asserts in kernel code with ASSERT
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-05-17 10:18:16 -03:00
Tiago Medicci Serrano
a00fbbeb9f espressif: Add option to disable the GIT_DEPTH to pull submodules
By default, submodules are cloned with `--depth=1`. This continues
to be true if `DISABLE_GIT_DEPTH` environment variable is not
defined (and it is not defined by default). But, if defined the
submodules will be fully cloned (without the `--depth` parameter).
2024-05-17 19:10:46 +08:00
Jukka Laitinen
9257af55f1 risc-v/mpfs: Change linker symbols _ssbi_ddr and _esbi_ddr into _ssbi_ram and _esbi_ram
The original names are confusing; the symbols' addresses point to the start and end of the
sbi executable ram area. This may also reside in l2lim and not in ddr, depending on the
configuration, and this is defined in the linker script.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-05-16 17:14:43 -03:00
Tiago Medicci Serrano
8a37d1ff1c espressif: Minor changes to keep consistency between sources
This commits replicates some changes on files that were originally
written for other Espressif SoCs and inspired new implementations.
Eventually, these new implementations were improved and this commit
replicates these changes on the original sources.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
c412dadcb9 esp32c3/wifi: Add support for the Wi-Fi in ESP32-C3
This commit introduces support for both station and softAP modes.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
7ed64e7234 esp32c3: Substitute / to $(DELIM)
Substitute `/` to `$(DELIM)` to make it compatible with other
implementations.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
2c4963dcd6 esp32c6/wifi: Add support for the Wi-Fi in ESP32-C6
This commit introduces support for both station and softAP modes.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
9e8c9ea47f esp: Update libc stubs to properly acquire/release locks.
Avoid using static mutex and recursive mutex as the resource to be
acquired/release. Instead, create a specific lock for each call if
it does not exist.
2024-05-14 22:10:45 +08:00
Tiago Medicci Serrano
47b0cae778 esp/hr_timer: Fix issue with timed-out timers 2024-05-14 22:10:45 +08:00
simbit18
d1789d84e8 fix nxstyle
fix Relative file path does not match actual file.
2024-05-13 22:24:36 +02:00
Inochi Amaoto
4d2d9ecf39 arch/risc-v: fix idle stack assign order
The bc022f8cd8 introduces a static way to calculate idle stack
address for risc-v platform. However, it uses the reverse order
to access idle stack, which breaks boards with smp configuration.

Correct the idle stack order of g_cpux_idlestack.

Fixes: bc022f8cd8 ("arch/risc-v: unify idle stack calculation")
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-12 15:22:50 +09:00
Inochi Amaoto
bc022f8cd8 arch/risc-v: remove g_cpux_idlestack
As all the board allocate idle stack from _ebss. The idle stack
layout is fix and can be computed directly by using _ebss. There
is no need to use g_cpux_idlestack array anymore, remove it.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-11 17:57:59 +02:00
Inochi Amaoto
afb5a66847 arch/risc-v: unify idle stack calculation
As the stack layout is unified, it is possible to
use a unify formula to calculate the top of idle
stack.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-11 17:57:59 +02:00
simbit18
09bfaa7292 fix nxstyle
fix Relative file path does not match actual file.
2024-05-11 01:19:06 +08:00
hujun5
5cee996588 up_putc: int up_putc, enter_critical_section may be called
before kernel has been iniitialized,we use spin_lock_irqsave to replace.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-09 13:45:02 +08:00
Inochi Amaoto
f4a38c01df arch/risc-v: Make esp32 SoCs allocate idle stack after ebss
ESP32 SoC use a static allocated array as idle stack. To fit
the existed idle stack allocation, make idle stack allocated
from ebss for the whole esp32 series.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-08 15:43:41 +08:00
Yanfeng Liu
ef15b5296d riscv/virt: M-mode poweroff support
This adds poweroff support to `rv-virt/nsh` and `rv-virt/nsh64`.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-08 15:39:26 +08:00
Yanfeng Liu
c352b04155 risc-v/sbi: add SRST extenstion usage in S-mode
This adds SBI specfication v0.3 based `riscv_sbi_system_reset()` to
support SBI firmware based system reset in kernel mode.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-05-07 21:02:49 +08:00
chenwen@espressif.com
3a9d163aae esp32_c3/pm: Fix assert issue in PM mode
1. Adjust code to avoid PM wakelock->count less than or equal to 0.
    2. Fix some document format issues.

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-05-07 15:45:32 +08:00
Inochi Amaoto
04e40182ad arch/risc-v: Make bl602 allocate idle stack after ebss
Although almost all board support allocating idle stack after ebss,
bl602 have a different memory layout for idle stack. To unify them,
make idle stack allocated from ebss for bl602.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-06 15:04:24 -03:00
Ville Juven
0cd5689bcb riscv/pgmap: Fix bug in kernel page directory init
The L2 table was not connected -> results in random crashes. Also add
missing data sync barrier to the end.
2024-05-03 23:49:11 +08:00
Inochi Amaoto
bd895222eb arch/risc-v: implement sbi_ipi_send
And SBI ipi support.

Fixup: 4f63ca1418 ("arch/risc-v: unfiy IPI access)
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-02 16:08:13 +08:00
Inochi Amaoto
b283b949b6 arch/risc-v: implement standard ecall interface for nuttsbi
NuttSBI have a simple ecall interface for the kernel, which make
it hard to add new SBI call for NuttSBI. So implement standard
ecall interface for NuttSBI and make life easier.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-05-02 16:08:13 +08:00
chao an
8821a0396a arch/risc-v: correct minor issues regarding comments
The comment in riscv_vpu.S should be vector not floating

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-30 17:26:57 +08:00
Eren Terzioglu
891d67bb5e esp32[c3|h2|c6]: Add support to TWAI/CANBus controller 2024-04-30 10:03:22 +08:00
Philippe Leduc
3dc6b4c9bd Add basic support for locales in order to C++ streams to build and work for simple cases (POSIX / C locale).
Fix build with C++ GCC toolchain
2024-04-29 17:34:10 +08:00
Inochi Amaoto
c148e8f2af arch/risc-v: Fix typo in riscv_set_inital_sp
Set right name for the parameter description of riscv_set_inital_sp.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-28 17:24:31 +08:00
Inochi Amaoto
49b3f52db1 arch/riscv/qemu-rv: replace M-mode init code with SBI in kernel build
The qemu-rv use a small init code for M mode in kernel build.
It is hard-coding and is difficult to change. Due to the fact,
introduce a already mature SBI implement (e.g OpenSBI) to
replace existing code is a better choice.

This patch introduce some change for qemu-rv:
1. use SSTC to provide time interrupt in kernel build
2. remove uncessary M mode trap.

For simplicity, this patch does not add support for booting
nuttx for any core, but force boot core to start core 0 and
let core 0 do the initialization.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
3cabc92427 arch/risc-v: add risc-v SSTC extension support
SSTC extension allows nuttx to implement S-mode timer directly,
which is useful for starting at S-mode.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
1d7afb571f arch/risc-v: report correct interrupt stack base
As `up_get_intstackbase` supports per cpu stack base, fix
the report value with the cpu specific one.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
a33313413d arch/risc-v: introduce dynamic stack allocation.
It is misleading to allocate stack from static array and heap,
make all stack allocated from heap area.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
Inochi Amaoto
1ef3767f85 arch/risc-v: unfiy IPI access
Add ipi process abstract function support.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-27 22:09:22 -03:00
chao an
1f7147129a arch/risc-v: fix break on kernel mode
merge conflicts lead to incorrect ifdef/endif scope

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-26 12:44:57 +09:00
chao an
a51ebeab4b arch/risc-v: decouple Per-CPU scratch with ARCH_USE_S_MODE
In some special chipsets, multiple CPUs may be bundled in one hardware
thread cluster, which results in hartid and cpuindex not being exactly
the same. The new option will decouple Scratch-based Per-CPU storage
with S-Mode to distinguish the real cpu index.

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-25 09:48:59 -03:00
chao an
da4c229312 arch/riscv: replace atomic operations to AMO
RISC-V provided fetch-and-op style atomic primitives as they scale
to highly parallel systems better than LR/SC or CAS. A simple
microarchitecture can implement AMOs using the LR/SC primitives,
provided the implementation can guarantee the AMO eventually
completes. More complex implementations might also implement AMOs
at memory controllers, and can optimize away fetching the original
value when the destination is x0.

Signed-off-by: chao an <anchao@lixiang.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2024-04-25 18:23:58 +09:00
chao an
6086b1410b arch/risc-v: remove the hard code array of cpu idle stack
Do not limit the number of CPU idle stacks by hard code

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-24 11:58:19 +08:00
Yanfeng Liu
5c3fc2796b tools/export: fix names for app linker script and program entry.
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.

flat and protected mode should be the same as before.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-24 11:40:16 +08:00
chao an
28044f7d5a arch/risc-v: add support of save/restore vector registers
Reference:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/vector.h

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-23 16:18:46 -03:00
chao an
4b086f595e arch/risc-v: rename local variable name to avoid shadowed declaration
In file included from common/addrenv.h:33,
                 from common/riscv_initialstate.c:36:
common/riscv_initialstate.c: In function 'up_initial_state':
common/riscv_internal.h:136:16: warning: declaration of 'regval' shadows a previous local [-Wshadow]
  136 |      uintptr_t regval; \
      |                ^~~~~~
common/riscv_initialstate.c:74:12: note: in expansion of macro 'READ_CSR'
   74 |   regval = READ_CSR(CSR_VLENB);
      |            ^~~~~~~~
common/riscv_initialstate.c:63:13: note: shadowed declaration is here
   63 |   uintptr_t regval;
      |             ^~~~~~

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-22 16:22:51 +08:00
chao an
d59f9186ca arch/risc-v: add llvm experimental extensions into command line
LLVM supports (to various degrees) a number of experimental extensions.
All experimental extensions have experimental- as a prefix. There is
explicitly no compatibility promised between versions of the toolchain,
and regular users are strongly advised not to make use of experimental
extensions before they reach ratification.

Fix compile error:
riscv64-unknown-elf-clang: error: invalid arch name 'rv64gcv_zfh_zvfh', requires '-menable-experimental-extensions' for experimental extension 'zvfh'

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-19 20:13:54 +08:00
chao an
e863e3dd37 arch/risc-v: add LLVM clang support
Verified on LLVM-Metal:
$ riscv64-unknown-elf-clang --version
(LLVM-Metal 15.9.0-2023.03.0) clang version 15.9.0
Target: riscv64-unknown-unknown-elf
Thread model: posix

Signed-off-by: chao an <anchao@lixiang.com>
2024-04-19 12:27:56 +08:00
Huang Qi
93d75129de riscv: Add Vector CSRs to csr.h
The CSR register definitions from RVV 1.0 spec: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-registers

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-19 00:31:07 +08:00
Almir Okato
f4bbe276e1 esp32[c3|c6|h2]: Fix simple boot map_rom_segments
Currently Simple Boot image have fixed 2 ROM segments and
2 RAM segments, then the parsing iterator must stop when all
ROM segments are found.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-04-17 00:09:58 +08:00
Yanfeng Liu
200424e59d arch/risc-v: fix RV32 up_addrenv_destroy
This patch fixes the issue/12122 for RV32, where the scanning should be
limited to user space only.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-14 14:49:36 +08:00
Jakub Janousek
3ce84d1ba0 arch and board esp32c3-legacy: Add optional iCE40 FPGA loading support
Signed-off-by: Jakub Janousek <janouja9@fel.cvut.cz>
2024-04-12 10:19:58 -03:00
Inochi Amaoto
412d2ce113 arch/riscv: add T-HEAD CSR mapping
Add T-HEAD CSR mapping file.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-11 22:20:39 +08:00
Inochi Amaoto
bae686e127 arch/riscv: force using encoding macro for CSR access
Using CSR name depends on compiler support heavily, but CSR
encoding does not have this problem. It also make it easy to
add new CSR support even if the compiler does not support.

Unify CSR access by using the CSR encoding macro.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-04-11 10:43:48 +08:00
Huang Qi
9e78b235fe riscv: Add more debug related CSR definitions
This patch adds more debug related CSR definitions
to arch/risc-v/include/csr.h.

These definitions are from the RISC-V Debug Specification
Version 1.0 rc1 (https://github.com/riscv/riscv-debug-spec).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-10 21:10:39 +08:00
ligd
3844efb5b8 stack: update up_get_intstackbase API to support cpu id
For crash dump all the CPU intstack

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
simbit18
9967989b02 Fix Kconfig style
Remove spaces from Kconfig files
Remove TABs
Add comments
2024-04-09 10:49:23 +08:00
Eren Terzioglu
c0d7419d11 esp32[c3|h2|c6]: Bugfixes for filesystem errors 2024-04-09 10:48:40 +08:00
W-M-R
0ede3fc377 kasan: Implementing global variable out of bounds detection
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module

Signed-off-by: W-M-R <mike_0528@163.com>
2024-04-07 23:31:13 +08:00
Tiago Medicci Serrano
65bd548521 esp32[c3|c6|h2]: Fix RTC data placement
RTC data was not being correctly placed on RTC's memory data due to
linker issues. Also, the image's RTC memory segment was not being
properly parsed by the bootloader.
2024-04-05 02:50:19 +08:00
Eren Terzioglu
19b58a78da risc-v/espressif: Fix empty cpuint number 2024-04-02 16:40:24 -03:00
Tiago Medicci Serrano
9520edeb16 espressif/rmt: Fix minor issues regarding formatting and comments
This commit only fix minor issues regarding formatting and comments
2024-04-02 14:50:59 -03:00
Yanfeng Liu
3a59644485 build/cmake: kernel mode revision
This fixes kernel mode regression caused by #12011

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-30 12:21:59 +08:00
xuxin19
741de4b450 cmake:init protected-mode for CMake build
adjust link options for userspace elf
specify system libs and apps lib to only link with nuttx target in flat build mode

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-03-27 23:01:08 +08:00
Eren Terzioglu
f5030573b7 esp32[c3|c6|h2]: Fix filesystem test support 2024-03-26 20:56:48 +08:00
Eren Terzioglu
d322140464 boards/esp32c6: Add esp32c6 DevKitM board support 2024-03-26 09:43:08 +08:00
Eren Terzioglu
cfcedab76b arch/espressif: Fix esp32c6 strange characters on boot 2024-03-26 09:39:12 +08:00
Yanfeng Liu
56b125bb82 risc-v/arch.h: revising comments
This revises comments about page tables to help understanding.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-25 20:39:24 +08:00
Jukka Laitinen
1f6079814a arch/risc-v/src/common/supervisor/riscv_perform_syscall.c: Record the currently running task in risc-v syscall
If a context switch occurs in syscall, the g_running_task need to be recorded for assert logic.
This copies the logic from arm platforms

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-21 18:45:41 +08:00
Jukka Laitinen
f1c877d67d arch/risc-v/src/common/riscv_exception.c: Just _exit the user task causing an exception
We shouldn't panic the kernel when a user task excepts, we can just kill the user task and
it's children. Do this by returning to _exit() in kernel context.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-20 18:03:15 -03:00
Stuart Ianna
401b3e682c arch/risc-v/litex: Allow FDT to be passed from previous boot change.
Allows a flattened device tree to be passed from either openSBI or the LiteX bios. The FDT is registered can be used, if supported.
2024-03-20 20:53:17 +08:00
Yanfeng Liu
ea8682572c build/cmake: add initial KERNEL mode support
Currently only FLAT mode development can enjoy cmake build system. This
patch tries to add initial kernel mode support. It can build NuttX kernel
and libproxies.a, the latter will be further checked though.

This can already help to build an AMP remote node image as it can share
userland apps living in the AMP master node.

Major changes:

- in top folder:
  - CMakeLists.txt    adjust for KERNEL mode, separate from PROTECTED mode.
- in `syscall`:
  - CMakeLists.txt    add mksyscall target for stubs/proxies generation
- in `syscall/stubs`:
  - CMakeLists.txt    use dependency to mksyscall
- in `syscall/proxies`:
  - CMakeLists.txt    use dependency to mksyscall
- in `arch`:
  - CMakeLists.txt    separate KERNEL from PROTECTED mode.
- in `arch/risc-v/src`:
  - CMakeLists.txt    separate from PROTECTED mode, add sub folders.
- in `arch/risc-v/common`:
  - CMakeLists.txt    add sources and sub-folders for KERNEL mode.
- in `arch/risc-v/k230`:
  - CMakeLists.txt    add sources for KERNEL mode.
- in `boards/risc-v/k230/canmv230/src`:
  - CMakeLists.txt    adjust k230 specific scripts for kernel mode.

New additions:

- in `arch/risc-v/src/nuttsbi/`           add CMakeLists.txt
- in `arch/risc-v/src/common/supervisor/` add CMakeLists.txt

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-15 16:21:23 +08:00
Yanfeng Liu
ea7dbdc8ac risc-v/k230: fix k230_hart_is_big issue
This patch fixes the issue that k230_hart_is_big() doesn't work in
S-mode. It also adds convenient debug macros to ease debugging process

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-14 00:05:06 +08:00
Yanfeng Liu
1fa2559f00 riscv/k230: add ARCH_HAVE_RESET revise logging
This patch adds board_reset and revises debug logging.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-13 13:46:02 +08:00
Eren Terzioglu
11efa29192 esp32h2/scripts: Add simpleboot support for esp32h2 2024-03-09 11:53:47 +08:00
Eren Terzioglu
11a061cad8 esp32c6/scripts: Add simpleboot support for esp32c6 2024-03-09 11:53:47 +08:00
Yanfeng Liu
02d097ac4d riscv/k230: minor revision on PMP settings
This patch simplifies PMP handling for K230 using common APIs.
It also uses `g_misa` variable to expose the MISA issue.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-09 11:52:13 +08:00
Xiang Xiao
64ea027b1a Replace PRIxPTR with %p and remove the cast of (uintptr_t)
The cast of (uintptr_t) is not necessary, and it is better to use %p

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-03-07 09:59:42 -03:00
Yanfeng Liu
cc389b1984 riscv/nuttsbi: revise PMP manipulation in NuttX SBI
Current NuttX SBI assumes empty PMP settings but that is not always
true, for example some bootloaders may have PMP entries locked before
handling over to NuttX. This patch revises it by not using hardcoded
PMP region number.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-07 09:58:55 -03:00
Yanfeng Liu
a66c7c3ee1 comments/docs: fix typos in comments
This fix some typos in comments.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-06 13:31:50 +08:00
trns1997
54e9e582d5 Use C++ standard lib from toolchain
Signed-off-by: trns1997 <trns1997@gmail.com>
2024-03-06 08:42:44 +08:00
Tiago Medicci Serrano
c67502d9b4 riscv: Implement page-fault exception and on-demand paging
When an application is being loaded `up_addrenv_create ` calls
`create_region` to create the address environment. Only the first
entry is mapped when the region is created. Virtual memory that is
not mapped will trigger an exception when accessed. Other memory
pages are allocated and mapped on-demand. This enables setting
larger heap and stack for the process without compromising the
overall system memory.
2024-03-05 09:45:49 +08:00
Yanfeng Liu
a4d61dea80 risc-v/k230: improvements to support K230 vendor u-boot
Previously we need turn off the PMP locks in K230 vendor u-boot to use
NuttX, this complicates the setup process. This patch supports running
NuttX with original vendor u-boot so that to reduce setup complexity.

It also enables empty NSH prompt string in AMP master config as the apps
side support is ready.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-03 12:04:14 -03:00
Marco Casaroli
447cc9698f use apps-or-nuttx-Make.defs for archs
This will allow apps to tweak build configuration of NuttX
2024-03-01 12:59:16 -03:00
ligd
2241969e5a SMP: fix crash when switch to new task which is still running
cpu0 thread0:                        cpu1:
sched_yield()
nxsched_set_priority()
nxsched_running_setpriority()
nxsched_reprioritize_rtr()
nxsched_add_readytorun()
up_cpu_pause()
                                     IRQ enter
                                     arm64_pause_handler()
                                     enter_critical_section() begin
                                     up_cpu_paused() pick thread0
                                     arm64_restorestate() set thread0 tcb->xcp.regs to CURRENT_REGS
up_switch_context()
  thread0 -> thread1
arm64_syscall()
    case SYS_switch_context
     change thread0 tcb->xcp.regs
    restore_critical_section()
                                     enter_critical_section() done
                                     leave_critical_section()
                                     IRQ leave with restore CURRENT_REGS
                                     ERROR !!!

Reason:
As descript above, cpu0 swith task: thread0 -> thread1, and the
syscall() execute slowly, this time cpu1 pick thread0 to run at
up_cpu_paused(). Then cpu0 syscall execute, cpu1 IRQ leave error.

Resolve:
Move arm64_restorestate() after enter_critical_section() done

This is a continued fix with:
https://github.com/apache/nuttx/pull/6833

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-01 21:05:00 +09:00
chao an
6d50274ebe nuttx/list: rename container_of to list_container_of from public header
Use private naming to avoid conflicts with user applications

In file included from libuv/src/unix/internal.h:25,
                 from libuv/src/unix/udp.c:23:
libuv/src/uv-common.h:57: warning: "container_of" redefined
   57 | #define container_of(ptr, type, member) \
      |
In file included from nuttx/include/nuttx/list.h:47,
                 from nuttx/include/nuttx/tls.h:40,
                 from nuttx/include/nuttx/sched.h:48,
                 from nuttx/include/nuttx/arch.h:87,
                 from nuttx/include/nuttx/userspace.h:35,
                 from nuttx/include/nuttx/mm/mm.h:30,
                 from nuttx/include/nuttx/kmalloc.h:34,
                 from nuttx/include/nuttx/lib/lib.h:31,
                 from nuttx/include/stdio.h:35,
                 from apps/system/libuv/libuv/include/uv.h:59,
                 from libuv/src/unix/udp.c:22:
nuttx/include/nuttx/nuttx.h:48: note: this is the location of the previous definition
   48 | #define container_of(ptr, type, member) \
      |

Signed-off-by: chao an <anchao@lixiang.com>
2024-02-29 19:44:54 +08:00
Eren Terzioglu
aa0dccb7bc risc-v/espressif: Add SPI Flash support 2024-02-21 07:19:51 -08:00
Yanfeng Liu
4456b2db29 risc-v/k230: add IPI support to speed up RPTUN/RPMSG
This patch adds inter-processor interrupt support using K230 mailbox
device to improve the RPMsg efficiency. The polling logic has been
dropped.

Major changes:

- in arch/risc-v/include/k230:
  - irq.h          add IRQ for IPI devices
- in arch/risc-v/src/k230:
  - Kconfig        add IPI related config, increase polling delay
  - Make.defs      add k230_ipi.c to CHIP_SRCS
  - k230_hart.c    fix typo, add notes of zero MISA reading w/ NUTTSBI
  - k230_irq.c     use K230_PLIC_IRQS as ext IRQ limit to support IPI
  - k230_rptun.c   use IPI instead of polling
- in boards/risc-v/k230/canmv230/configs
  - master         enable IPI support
  - remote         enable IPI, TMPFS, RPMSGFS etc

New additions:

- in arch/risc-v/src/k230:
  - k230_ipi.h     add K230 IPI related defintions
  - k230_ipi.c     add K230 IPI driver

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-21 04:37:03 -08:00
chao an
f4bc5b5c6b cmake/toolchain: fix compiler warning on ARM32
-- Detecting CXX compile features
-- Detecting CXX compile features - done
arm-none-eabi-gcc: error:  -Wstrict-prototypes: No such file or directory
arm-none-eabi-gcc: error:  -Wstrict-prototypes: No such file or directory
-- Configuring done
-- Generating done

Signed-off-by: chao an <anchao@lixiang.com>
2024-02-21 00:43:42 -08:00
Tiago Medicci Serrano
e49684d781 risc-v/esp_<rmt|ws2812>: Implement the RMT peripheral for ESP32 RVs
This commit implements the RMT peripheral for all the supported
Espressif's RISC-V devices. It also implements the support for the
WS2812 addressable RGB LED using the RMT peripheral.
2024-02-19 19:02:34 -08:00
Xiang Xiao
2e91c07ca7 Remove the back slash from long literal string
since the back slash is only needed for the long macro definition

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-19 16:43:15 +01:00
freakishness
b283e39eb5 Add support for hpm6360evk 2024-02-18 09:17:56 -08:00
Yanfeng Liu
709a1c61f1 risc-v/k230: revise k230 hart operations and kernel linker script.
This patch revises `k230_hart.[ch]` by:

  - revising big core boot/stop control.
  - making k230_hart_is_big() available in S-mode.
  - adding more comments.

This patch also revises the `ld-kernel.script` so that to match the
latest MMU pgtable design.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-15 19:53:24 -08:00
Yanfeng Liu
a4b22fe999 risc-v/k230: initial Asymmetric Multi-Processing support
K230 chip has two T-Head C908 RiscV cores, previously we run NuttX
on either little or big cores. This patch runs NuttX on both cores
with OpenAMP support via the RPTUN driver.

New additions:

- in arch/risc-v/src/k230
  - k230_rptun.c              K230 RPTUN driver
  - k230_rptun.h              K230 RPTUN driver header file

- in baords/risc-v/k230/canmv230
  - configs/master            Build config for master node
  - configs/remote            Build config for remote node
  - scripts/ld-rptun.script   Build script for RPTUN

Major changes:

- arch/risc-v/Kconfig         Select NUTTSBI_LATE_INIT upon NUTTSBI
- in arch/risc-v/include
  - k230/irq.h                Add UART3 IRQ defs
- in arch/risc-v/src/k230
  - Kconfig                   Add RPTUN related config items
  - Make.defs                 Add k230-rptun.c to sources
  - hardware/k230_memorymap.h Add K230 device and CSR defs
  - k230_hart.c               Add hart ctrl for RPTUN
  - k230_hart.h               Add hart ctrl for RPTUN
  - k230_mm_init.c            Add Svpmbt to support RPTUN
  - k230_start.c              Revised to support RPMsg UART
- in boards/risc-v/k230/canmv230
  - scripts/Make.defs         Add RPTUN script selection
  - src/canmv_init.c          Add RPTUN and RPMsg_UART initialization
- in Documentation/platforms/risc-v/k230/boards/canmv230
  - index.rst                 Add AMP usage information.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-13 10:34:21 -03:00
Jukka Laitinen
888dc229fa arch/risc-v/src/mpfs/mpfs_serial.c: Allow switching uart output to console off
By setting "isconsole" to false, mpfs_serial stops outputting to console.

This can be used to disable output to debug console in low level.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:53:05 -08:00
Jukka Laitinen
a28f6716d5 arch/risc-v/src/mpfs/mpfs_irq.c: Fix up_irqinitialize for warm reboot
It is possible that a PLIC IRQ is claimed but not completed at warm
reset. This occurs at least if there is a fault in the middle of irq
handler execution.

To recover from such situation, we can complete all IRQ:s in PLIC;
this completes any already claimed IRQ, but has no effect on IRQs
which are not claimed or not enabled.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:46 -08:00
Jukka Laitinen
df01c83c25 arch/risc-v/src/mpfs/mpfs_i2c.c: Recover i2c from pending transactions in warm boot
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Jukka Laitinen
2b10b38c1d arch/risc-v/src/mpfs/mpfs_i2c.c: Add more i2cerr traces
Add sanity checks for debugging possible errors in the driver.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Jukka Laitinen
120dfbd45f arch/risc-v/src/mpfs/mpfs_i2c.c: Correct i2c reset / error recovery
- Use mpfs_i2c_deinit+mpfs_i2c_init sequence to re-initialize i2c block
- Use the i2c mutex to protect the reset; in case there are several devices
  on the same bus, and one of them resets the bus, reset must not occur in
  the middle of another device's transfer.
- Move irq attach to the i2c_init as the irq detach is in i2c_deinit

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Jukka Laitinen
fc4b39b1dd arch/risc-v/src/mpfs/mpfs_i2c.c: Add more error status codes
Add more error status codes to help debugging in the future.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Jukka Laitinen
dae31dc866 arch/risc-v/src/mpfs/mpfs_i2c.c: Clear I2C_CTRL bits when initializing/deinitializing bus
Ensure that there are no pending state or interrupts in the i2c controller. This removes
errors caused by deinitialize/initialize sequences in error cases.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Eero Nurkkala
bcf7aa4b63 risc-v/mpfs: i2c: perform sanity checks
Replace risky DEBUGASSERT()s with real sanity checks. Also,
do a few more checks as the system might occasionally fire an
interrupt if the system has been restarted while in middle of
an i2c transaction.

Yet, modify i2c_transfer() function so that up_disable_irq()
is always called at the end to better prevent ill-timed irqs.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-02-06 08:52:31 -08:00
Eero Nurkkala
b0cef9e008 risc-v/mpfs: i2c: prevent out of bounds read access
priv->msgid may grow past its boundaries, causing
struct i2c_msg_s *msg = &priv->msgv[priv->msgid]
to read data out of boundaris.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-02-06 08:52:31 -08:00
Xiang Xiao
ebc6924b26 risc-v/mpfs: Remove thee unused seq[s|m] fields
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
1e3914ec9d rptun: Remove the unused shmemname field and argument
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
6a6bd30500 rptun: Remove the empty implementation of get_firmware and get_addrenv
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
43d51cd4fc arch: Remove the identity mapping of up_addrenv_va_to_pa and up_addrenv_pa_to_va
and reuse the reuse the implementation from:
drivers/misc/addrenv.c

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Yanfeng Liu
73ecd741e7 risc-v/common: add param to mmu_flush_cache interface
Current mmu_flush_cache() hook lacks the reg param which needed by
some targets. So this PR adds the param and update existing targets
using that hook.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-03 22:05:42 -08:00
Ville Juven
15f19c32ac arch/addrenv: Add utility function to wipe one page
up_addrenv_page_wipe can be used to wipe a single page of memory.
2024-02-02 09:09:55 -08:00
Yanfeng Liu
6594439271 risc-v/nuttsbi: fix weak sbi_late_initialize issues
Weak function sometimes can't have strong implementation linked.
This patch uses NUTTSBI_LATE_INIT config and normal function instead
to avoid those issues.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-01 21:26:16 -08:00
Jari Nippula
e40b66bd6f risc-v/mpfs: wrapper for sdio device drivers
Additional mpfs_sdio layer on top of mpfs_emmcsd and mpfs_coremmc
block device drivers to let both block devices be enabled at the
same time.
2024-02-01 02:07:32 -08:00
Eren Terzioglu
d1db1810ad risc-v/espressif: Rename espressif/esp32c3 as esp32c3
risc-v/espressif: Rename espressif/esp32c6 as esp32c6
risc-v/espressif: Rename espressif/esp32h2 as esp32h2
2024-01-30 08:32:05 +01:00
Eren Terzioglu
c8d7c81cb9 risc-v/esp32c3: Rename legacy approach esp32c3 as esp32c3-legacy 2024-01-30 08:32:05 +01:00
Eren Terzioglu
4c4d62ff93 Rename espressif folder as common/espressif 2024-01-30 08:32:05 +01:00
Eren Terzioglu
721c37a876 risc-v/esp32c6: Remove duplicated esp32c6 implementation 2024-01-30 08:32:05 +01:00
Yanfeng Liu
0f169f50c4 risc-v/k230: add big core support
Previously NuttX runs on little core of K230, this patch allows NuttX to
run on the big core as well.

Within folder `arch/risc-v/src/k230`:

- Changes:

    - CMakeLists.txt      add k230_hart.c to sources list
    - Make.defs           add k230_hart.c to sources list
    - chip.h              add inclusion to k230_hart.h etc
    - k230_irq.c          move sbi_late_init() to k230_hart.c
    - k230_start.c        add support to run on big core
    - hardware/:
      - k230_memorymap.h  add T-Head C908 specific CSR

- Additions:

    - k230_hart.c         sbi_late_init w/ hart initialization
    - k230_hart.h         header file

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-29 09:06:28 +01:00
Yanfeng Liu
f69f0674f6 arch/risc-v: add status fields for VS and XS
add defintions for vector extension and additional user-mode
extension fields for MSTATUS and SSTATUS registers.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-28 06:38:25 -08:00
Yanfeng Liu
bb63f8f36d risc-v/canmv230: add CMake support
Adding CMakeLists.txt files to support CMake build system.
Note that only FLAT build works now due to limitations of current
CMake build system.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-27 00:56:57 -08:00
Ville Juven
a188cf3480 mpfs_corespi: Fix firing of stale interrupt after warm reset
After warm reset the interrupt source in the HW block is not explicitly
cleared, thus once the interrupt source is enabled the old / stale interrupt
fires immediately.

This causes a DEBUGASSERT() failure on line 808 mpfs_spi_unload_rx_fifo:
  DEBUGASSERT(nwords > 0);
2024-01-25 11:23:12 -03:00
Tiago Medicci Serrano
c4f76ff867 esp32c3: Fix building native MCUboot from sources
This commit fixes building native MCUboot from sources by getting
the required sources from `esp-hal-3rdparty` repository and enable
building MCUboot and using it as the 2nd stage bootlaoder.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
a2673d3bcd esp32c3: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32C3_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32C3_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
7ac14b544e risc-v/espressif: Select simple boot by default for RISC-V
Simple boot is a method of booting that doesn't depend on a 2nd
stage bootloader. Please note that some of the ESP-IDF bootloader
features are not available using simple boot, such as partition
tables and OTA: most of these features are implemented in NuttX
and MCUboot.
2024-01-25 11:22:39 -03:00
Almir Okato
f8b0b06b97 esp32c3-generic: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also makes this bootloader configuration as default
for esp32c3-generic target and removes the need for running
'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-01-23 04:09:25 -08:00
Lee Lup Yuen
62c358946d risc-v/bl808: Flush MMU Cache after updating SATP
Ox64 BL808 crashes with a Page Fault when we run `getprime` then `hello`. This is caused by the T-Head C906 MMU incorrectly accessing the MMU Page Tables of the Previous Process (`getprime`) while starting the New Process (`hello`).

To fix the problem, this PR flushes the MMU Cache whenever we point the MMU SATP Register to the New Page Tables. We execute 2 RISC-V Instructions that are specific to T-Head C906:

- DCACHE.IALL: Invalidate all Page Table Entries in the D-Cache
- SYNC.S: Ensure that all Cache Operations are completed

This is derived from the T-Head Errata for Linux Kernel. More details here: https://lupyuen.github.io/articles/mmu#appendix-flush-the-mmu-cache-for-t-head-c906

Modified Files:

- `arch/risc-v/src/common/riscv_mmu.h`: If needed, `mmu_write_satp()` calls `mmu_flush_cache()` (weak function) to flush the MMU Cache. (Like for T-Head C906)

- `arch/risc-v/src/bl808/bl808_mm_init.c`: Flush the MMU Cache for T-Head C906. Extend `mmuflags` from 32-bit to 64-bit to be consistent with `mmu_ln_setentry()`.

- `boards/risc-v/bl808/ox64/configs/nsh/defconfig`: Enable `ostest` in the Build Config. Update `CONFIG_BOARD_LOOPSPERMSEC` according to `calib_udelay`.
2024-01-23 01:25:20 -08:00
Yanfeng Liu
cba993df85 risc-v/cmake: add support to Ubuntu stock toolchain
Ubuntu stock toolchain `gcc-riscv64-unknown-elf` complains about
current CMake system (see issue#11573). This tries to fix it so
that both newer XPack and stock toolchains can be used with CMake.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-23 01:23:44 -08:00
chao an
02acf2d2a4 risc-v/cmake: set nostdlib to c compiler
To avoid build break:

ld: riscv-none-elf/lib/rv64imafdc_zicsr/lp64d/crt0.o: in function `.L0 ':
(.text+0x8): undefined reference to `__bss_start'
ld: (.text+0x10): undefined reference to `_end'
ld: (.text+0x36): undefined reference to `main'
collect2: error: ld returned 1 exit status

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-18 09:53:53 +01:00
chao an
2fd95611cb risc-v/cmake: configurable vendor ISA extensions
merge below commit into cmake:

1. risc-v/toolchain: configurable vendor ISA extensions

This option allows the platform to enable some vendor-customized ISA extensions,
E.g OpenHW, SiFive, T-Head.

SiFive Intelligence Extensions:
    SiFive Vector Coprocessor Interface(VCIX): xsfvcp
    SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf
    SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq
    SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq
Command Line:
    xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1

2. "V" Standard Extension for Vector Operations
3. "Q" Standard Extension for Quad-Precision Floating-Point

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-18 09:53:53 +01:00
Yanfeng Liu
1e9434e2db arch/: remove duplicated task exit logs
Newly added logging in `sched/task_exit.c` obsoletes the existing
ones in `arch/up_exit()`, thus remove the latter to reduce duplications.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-17 09:18:17 -08:00
Yanfeng Liu
87c9a0ee76 risc-v/k230: add NUTTSBI based kernel build support
Previously k230 kernel build needs OpenSBI wrapping for use on
target, thus leading to larger program and memory overheads.
This patch adds alternative small overhead kernel build support.

Changes:

- in arch/risc-v/src/k230:
  - k230_head.S          entrance renamed for sake of NUTTSBI
  - k230_irq.c           add M-mode handling for NUTTSBI case
  - k230_mm_init.c       add L3 table for smaller RAM case
  - hardware/k230_plic.h add PLIC_CTRL definition
  - Make.defs            use CHIP_ASRCS to fix entrance selection
- in boards/risc-v/canmv230/scripts:
  - Make.defs            add support for NUTTSBI case

Additions:

- in boards/riscv/canmv230/:
  - scripts/ld-nuttsbi.script  link script for NUTTSBI case
  - configs/nsbi/defconfig     config for NUTTSBI case

The artifact nuttx.bin from this configuration can be used directly
on target as OpenSBI wrapping is not needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>

fix typo
2024-01-17 10:31:29 -03:00
chao an
95fcc286a2 risc-v/toolchain: configurable vendor ISA extensions
This option allows the platform to enable some vendor-customized ISA extensions,
E.g OpenHW, SiFive, T-Head.

SiFive Intelligence Extensions:
    SiFive Vector Coprocessor Interface(VCIX): xsfvcp
    SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf
    SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq
    SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq
Command Line:
    xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
ce201bba61 risc-v/kconfig: move ARCH_HAVE_MMU into mmu type define
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
52e99bc66b risc-v/toolchain: move zicsr/zifencei extension into Kconfig
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
f95bbb2949 risc-v/toolchain: add "V" Standard Extension into command line
"V" Standard Extension for Vector Operations

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
chao an
3ee4227668 risc-v/toolchain: add "Q" Standard Extension into command line
"Q" Standard Extension for Quad-Precision Floating-Point

Signed-off-by: chao an <anchao@lixiang.com>
2024-01-15 22:31:39 -08:00
Yanfeng Liu
78e8c0dea5 risc-v/nuttsbi: add device specific initialization hook
Some devices have special preparations before entering S-mode, thus
a hook is needed from NUTTSBI to give them the chance.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-14 01:28:10 -08:00
Yanfeng Liu
f221878204 risc-v/nuttsbi: use ARCH_RV_MMIO_BITS for mtimer access selection
Chips like K230 has ARCH_RV64 but only supports 32-bit MMIO. So using
ARCH_RV_MMIO_BITS is more proper here.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-11 21:48:44 -08:00
Ville Juven
983387e6dd mpfs_mpucfg.c: Add mpfs_mpu_lock()
Add method to lock an MPUCFG entry. Locking means the value of the register
cannot be changed until the SoC is reset.
2024-01-11 06:57:16 -08:00