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916 Commits

Author SHA1 Message Date
Alan C. Assis
03738622a1 esp32s2: Add RNG driver support and board profile example 2021-10-23 04:03:12 -05:00
zhuyanlin
cf1a04d0a2 xtensa:cache: add lock & unlock feature 
Since some xtensa cores cache support lock & unlock feature.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-10-22 13:31:32 -03:00
Abdelatif Guettouche
8288a04a0b arch/xtensa/esp32: Remove the AES test from the driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-19 18:41:57 -03:00
zhuyanlin
b5134565fa arch:xtens:mpu: modify acc and memtype to uint32_t 
The uint8_t and uint16_t will overflow in MPU_ENTRY_AR marco.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-10-19 00:24:31 -05:00
Xiang Xiao
91398e73eb arch/xtensa/Kconfig: add quotes in source to clean warnings from setconfig 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-10-19 00:33:51 +02:00
Abdelatif Guettouche
7b43d11435 esp32_spiflash.c: Allocate only one variable to hold the cache state in 
single CPU mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
f54a929001 esp32_spiflash.c: Keep the index of the other CPU between SPI Flash 
operations.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
eeb68bda3d xtensa_testset.c: Simplify the test-set function and remove some old 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
dfe1637864 esp32_spiflash.c: Pause the other CPU during flash operation. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
f2c2323642 esp32_intercpu_interrupt.c: Force the functions to internal SRAM. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 22:56:21 -07:00
Abdelatif Guettouche
d2bc011719 arch/xtensa/xtensa_cpupause.c: Allow a spin before taking the g_cpu_wait 
spinlock.

If we repeatedly call up_cpu_pause and up_cpu_resume, there would be
cases where the next call to up_cpu_pause happens while the other CPU is
still responding to the previous resume request.  In this case the
DEBUGASSERT will trigger.  We should allow the first CPU to wait until the
other CPU has finished responding to the resume request.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 09:46:23 -07:00
Abdelatif Guettouche
591c1563b8 esp32_oneshot_lowerhalf.c: Use the same alignment as the rest of the 
code base.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
9e1d2ca95e esp32_rt_timer.c: Group static variables into a struct and fix naming 
standard

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0dff3f2762 esp32_wifi_adapter.c: Use the specified spin lock when 
enabling/disabling interrupts.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
a50d673df7 esp32_wifi_adapter.c: Don't hold another spinlock when calling 
enter_critical_section, we already hold the global IRQ spinlock.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
11216257cf esp32_rt_timer.c: Don't nest calls to spin_lock_irqsave with a device 
specific spinlock, this will lead to deadlocks.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e847c61801 esp32_wifi_adapter.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
32f7471f9e esp32_wlan.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
4ae1285124 esp32_emac.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
e64390d5e9 esp32_rt_timer.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
c61009c2cf esp32/esp32_spi_slave.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
2273684cb1 esp32/esp32_spi.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0123243f9a esp32/esp32_i2c.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
0af9a49d9c esp32/esp32_oneshot_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
698af43d78 esp32/esp32_freerun.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
04bd27400a xtensa/esp32_wdt_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Abdelatif Guettouche
19a096cdfe arch/xtensa/esp32_tim_lowerhalf.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Gustavo Henrique Nihei
ff705586bb xtensa/esp32s2: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei
4d5e0f8fe1 xtensa/esp32: Provide SPI Flash parameters to MCUboot build 
Also unify bootloader config creation to reduce duplication.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-10-15 23:55:10 -07:00
Abdelatif Guettouche
a7d8d9dd98 esp32s2/tie.h: Run the file though detab. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
6d246eb18f esp32s2/tie.h: The old tie.h file was from ESP32 which doesn't apply to 
ESP32-S2.  This commit gets the correct S2 tie.h file

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
217fd97fd3 xtensa_coproc.S: Correctly save/restore coprocessor0 state. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
7420f245bc xtensa_context.S: Save and restore SCOMPARE1 when necessary. 
SCOMPARE1 is used by some atomic instructions and need to be preserved
during a context switch.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-14 06:32:17 -03:00
Alan C. Assis
867c6d0636 esp32: Add initial support to Bluetooth Low Energy 
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
Co-authored-by: Gustavo Henrique Nihei <gustavonihei@gmail.com>
 2021-10-04 15:10:37 -03:00
Abdelatif Guettouche
d22b4ec539 espxx_rng.c: Add "/" at the beginning of paths for consistency. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
5c6a30c00b esp32_rng.c: Remove the initialization guard. The init function is 
called only once during startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Abdelatif Guettouche
6a262c5203 esp32_rng.c: Remove unused functions. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-30 13:50:25 -03:00
Sara Souza
8a142f474e xtensa/esp32-s2/rttimer: Disable alarm before setting a new value and enabling it 2021-09-28 21:02:57 -03:00
Alin Jerpelea
15a37c5a5a arch: Omni Hoverboards: update licenses to Apache 
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei
a5f9e29d78 xtensa/esp32s2: Enable support for "make bootloader" target 
This enables the provisioning of the bootloader binaries through the
build system.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:21:53 -07:00
Gustavo Henrique Nihei
800678ca78 xtensa/esp32s2: Enable booting from MCUboot bootloader 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-27 18:21:53 -07:00
Abdelatif Guettouche
5336704c77 esp32_start.c: Initialize the SPI RAM before enabling its cache. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-27 05:13:51 -07:00
Gustavo Henrique Nihei
c23986ec63 xtensa/esp32: Select ARCH_HAVE_BOOTLOADER for ESP32 chips 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei
4ac3044cc3 xtensa/esp32: Enable build system to download or build bins from source 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-23 20:52:25 -07:00
Abdelatif Guettouche
f2f2040c44 esp32_spiram/psram/himem: Add and fix the files' sections. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Abdelatif Guettouche
3d8a6fb676 esp32_spiram.c: Remove esp_himem_reserved_area_size from esp32_spiram.c 
file.  This function is already defined in esp_himem and is used only
when that file is built.  We don't need another weak function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Abdelatif Guettouche
2834d2a46f esp32_spiflash.c/esp32_spiram.c: Remove some unused macros/functions/variables. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-23 02:49:11 -07:00
Sara Souza
962059f843 xtensa/esp32-s2: Adds oneshot device driver support 2021-09-22 22:53:54 -03:00
Sara Souza
fba6fa2dc1 xtensa/esp32-s2: Adds support to rt_timer and systimer to ESP32-S2. 2021-09-22 17:18:24 -03:00
Sara Souza
2cd4f4af79 xtensa/esp32-s2: Adds freerun timer wrapper 2021-09-22 09:38:10 -03:00
Gustavo Henrique Nihei
eca1f86294 arch/xtensa: Remove CODE qualifier for Xtensa-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
e13dd7dab9 arch/xtensa: Remove FAR qualifier for Xtensa-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei
58f87ef443 xtensa/esp32: Fix wrong position for ++ operator on I2C driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Abdelatif Guettouche
9f4d7e4767 xtensa_dumpstate.c: Fix the name of the TCB variable when dumping the 
backtrace.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-21 09:22:28 -03:00
Abdelatif Guettouche
15b68b9abb esp32_spiflash.c: Correctly disable APP's CPU cache. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-17 17:43:45 -03:00
Gustavo Henrique Nihei
b33ccd01cf xtensa/esp32: Make the semaphore timeout on I2C configurable 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-16 14:07:26 -03:00
zhuyanlin
7947e50f06 xtensa:backtrace: flush to stack when in interrupt 
The registers may be in window during interrupt.
Flush window stack to stack first.
And fix warning in build.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:53:35 -05:00
zhuyanlin
cdb441cc3f arch:xtensa:dumpstate: use sched_dumpstack 
Use sched_dumpstack instead. The backtrace infomation like

xtensa_user_panic: User Exception: EXCCAUSE=0009 task: hello
xtensa_registerdump:    PC: 202b32b8    PS: 00060030
xtensa_registerdump:    A0: a02acb87    A1: 20998d10    A2: ffffaaaa    A3: 12345678
xtensa_registerdump:    A4: a02ba26c    A5: 209949c0    A6: 20990994    A7: 00000258
xtensa_registerdump:    A8: a02b32af    A9: 20998cb0   A10: 0000000f   A11: 209949a0
xtensa_registerdump:   A12: a02be95c   A13: 20994980   A14: 00000003   A15: 209949d0
xtensa_registerdump:   SAR: 00000000 CAUSE: 00000009 VADDR: ffffaaaa
xtensa_registerdump:  LBEG: 00000000  LEND: 00000000  LCNT: 00000000
xtensa_registerdump:  TMP0: 202b1512  TMP1: 20998af0
sched_dumpstack: [BackTrace| 3|0]:  0x202acbae 0x202b232e 0x202b1912 0x202b19f5 0x202b24f1 0x202b152f    0x40023 0x202b32b0
sched_dumpstack: [BackTrace| 3|1]:  0x202acb87 0x202a86a4

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
6e0f84dc88 arch:xtensa: add up_backtrace support 
Up_backtrace can be backtrace from task or interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
3acdbef60d xtensa:arch: force up_getsp to inline 
Up_getsp may be not inline in gcc, thus get the sp
is up_getsp function's sp, not the caller function.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
zhuyanlin
583dce0b98 arch:xtensa: remove WSBITS/WBBITS to core.h 
Remove WSBITS/WBBITS macro to core.h as may be used by
arch common code.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-16 10:32:38 +08:00
Sara Souza
83a9c2b24b xtensa/irq.h: Fixes the routine that clears the processor interrupt 2021-09-13 17:01:49 -03:00
zhuyanlin
8e6fbe700e xtensa:dcache_clean: use DCACHE_LINZESIZE instead of DCACHE_SIZE 
Clean_dcache use DCACHE_LINZESIZE instead of DCACHE_SIZE in addr loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-09-13 14:38:57 +08:00
Abdelatif Guettouche
4ef859924b esp32_serial.c: Release the spinlock before calling uart_xmitchars, this 
functions will call esp32_txint again which leads to deadlock since
esp32_txint has already locked the spinlock.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-09 19:35:17 +09:00
Abdelatif Guettouche
b5bb1fb8a3 esp32_serial.c: Replace critical section by a device specific spin lock. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-09 19:35:17 +09:00
Abdelatif Guettouche
f47d28c108 esp32_serial.c: Don't fake an interrupt when interrupts are not 
suppressed.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-09-08 09:27:08 -03:00
zhuyanlin
26b4bb3075 xtensa:cache: fix typo error 
use addr instead of add
 2021-09-08 11:19:02 +02:00
zhuyanlin
7b5c39a9d3 arch:xtensa: add xtensa_cache code support 
Add xtensa_cache code support
 2021-09-07 13:33:31 +08:00
zhuyanlin
d6fe0f18f5 arch:xtensa: add XTENSA_CACHE config support 
Add support for XTENSA_HAVE_ICACHE & XTENSA_HAVE_DACHE
 2021-09-07 13:33:31 +08:00
Sara Souza
26397c6695 xtensa/esp32: Wi-Fi board logic refactoring. 
This commit removes the initialization of the Wi-Fi partition
from the Wi-Fi board logic and moves it to the SPI Flash board code.

It creates 2 different partition (one for Wi-Fi and one for general
use).

It also allows these partitions to be mounted over several FSs.
 2021-09-04 14:30:02 +08:00
zhuyanlin
fd9ce0137e arch:xtensa: add xtensa mpu support 
Add support for Xtensa Memory Protect Unit.

Change-Id: I27e2f05daae24429ef7513d843b4f217daeefa0d
 2021-09-02 09:17:26 -03:00
Sara Souza
8081228556 xtensa/esp32-s2: Adds support to the timer driver 
Only one more support for ESP32-S2 chip.
 2021-09-01 14:10:01 -03:00
Xiang Xiao
b0c782255c libxx: Change CXX_LIBSUPCXX to LIBSUPCXX 
align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-28 17:14:48 -03:00
zhuyanlin
9ea7676731 arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS 
The name used in Tensilica support file core-isa.h for all vendors is
`XCHAL_NUM_INTLEVELS`.
Use a new name may be confused by newer porting xtensa arch.

Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de
 2021-08-28 21:51:45 +02:00
Abdelatif Guettouche
1385ea7673 arch/esp32: Properly handle GPIO interrupt in SMP. 
The PRO CPU and APP CPU have different peripherals for GPIO interrupts.
Each CPU needs to allocate an interrupt and attach it to its GPIO
peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-27 13:24:00 +09:00
Kapil Gupta
ec99e11f5e esp32/softap: Enable the WPA2 by default to ask user password 
Signed-off-by: Kapil Gupta <kapil.gupta@espressif.com>
Co-author: Alan Carvalho de Assis <alan.carvalho@espressif.com>
 2021-08-26 13:26:57 +08:00
Abdelatif Guettouche
fc594c5d25 esp32_irq.c: Extend the CPU interrupt/peripheral map to include the 
status of the interrupt (enabled/disabled).

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
810ed19b8f arch/xtensa/esp32_irq.c: Enable/disable interrupts using the Interrupt 
Matrix.

This allows manipulating interrupts from both CPUs.  Internal interrupts
however, still need to be disabled/enabled by each CPU.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
a7abd56448 arch/xtensa: Move the Xtensa specific part of interrupts to 
xtensa/include/irq.h

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
470799b0b3 arch/xtensa/esp32_irq: Remove the map/unmap IRQ functions they are used 
only inside this file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
04cd520293 arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
79cc12c034 arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq. 
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
237aebb7e1 arch/xtensa/esp32_cpuint.c: Refactor retrieving the intmap and register 
address of a peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
02c17c3169 arch/esp32: Simplify the interrupt allocation process. 
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
eefe7ebe5f xtensa/esp32_cpuint: export only one function to allocate a CPU 
interrupt.

That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.

All the drivers are also updated with this API change.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
dbdec45049 arch/xtensa/src/common: Use irq_spin APIs in modifyregXX 
Replace enter_critical_section with spin_lock_irqsave.
Replace leave_critical_section with spin_unlock_irqrestore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 23:32:40 +08:00
Abdelatif Guettouche
5ff703d5d0 arch/*_testset: Fix few typos. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 00:20:20 +08:00
Abdelatif Guettouche
2925d4956b xtensa/esp32: Use up_cpu_index instead of this_cpu. 
this_cpu requires sched.h to be included.
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5d626f7267 xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs 
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
56a7f3b651 arch/xtensa/esp32: Update the drivers regarding the API change in IRQ 
handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5be9f24fe5 arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted. 
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
97dca8fe10 arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and 
irq.c

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
633cdf8e27 arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts. 
This map also keeps track of the CPU that attached the IRQ.  This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Sara Souza
e092c457e6 xtensa/lx7: Fix the CROSSDEV variable 2021-08-20 16:48:20 +02:00
Xiang Xiao
af72376773 fs: Remove magic field from partition_info_s 
since it is wrong and impossible to return file
system magic number from the block or mtd layer.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 09:19:52 -03:00
Abdelatif Guettouche
cd0f64d779 xtensa/irq.h: Add a macro to convert to an IRQ from a peripheral ID. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-18 10:49:58 -03:00
Abdelatif Guettouche
a220766d57 xtensa.h: Remove unused function prototype. 
ESP32 uses a different function to start the app CPU and no other xtensa
CPU uses this __cpu1_start function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-18 04:41:40 -07:00
Xiang Xiao
71269811ca mtd: Implement BIOC_PARTINFO for all drivers 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-16 10:08:26 -03:00
Abdelatif Guettouche
5b350f3a0f arch/*_reprioritizertr.c: Fix typos in comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-14 11:19:34 -07:00
Gustavo Henrique Nihei
1dfcc6ab49 xtensa/esp32: Enable boot from Espressif's port of MCUboot 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-08-13 08:44:20 -03:00
zhuyanlin
1a1b1cc2b4 arch:xtensa: replace include file from src/chip_xxx to chip.h 
Use chip.h as a standard include file, replace chip_xxx in src dir
 2021-08-12 16:18:35 +02:00
zhuyanlin
30a2338e92 arch:esp: create chip.h header for chip src code. 
Create chip.h header for esp src code.
 2021-08-12 16:18:35 +02:00
zhuyanlin
6d592256fb arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h 
Those header contain syntax not be recognize by gnu assembler.
 2021-08-12 16:18:35 +02:00
zhuyanlin
e333733053 xtensa:coproc: fix XTENSA_CP_ALLSET error in some case 
Consider follow coprocessor configuration case:

\#define XCHAL_CP_NUM                    1       /* number of coprocessors */
\#define XCHAL_CP_MAX                    2       /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK                   0x02    /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK              0x00    /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME                  "AudioEngineLX"
\#define XCHAL_CP1_IDENT                 AudioEngineLX
\#define XCHAL_CP1_SA_SIZE               208     /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN              8       /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX       1       /* coprocessor ID (0..7) */

In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.

Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
 2021-08-10 19:44:55 -07:00
Abdelatif Guettouche
054e284785 *_cpustart.c: Fix typos in function description. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-11 11:06:27 +09:00
Sara Souza
61ab4f9f14 xtensa/esp32: Fix the type of enum passed between functions in esp32_rtc_clk 2021-08-10 11:15:51 -03:00
Sara Souza
67d29e7537 xtensa/esp32: initialize RTC in case PM or RTC configs are not set, but RWDT is. 2021-08-10 11:15:51 -03:00
zhuyanlin
5820972727 arch:xtensa: add arch stdarg.h include file for xtensa 
Add arch/include/stdarg.h for xtensa.

Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56
 2021-08-09 17:58:25 -03:00
Xiang Xiao
776458143c fs/hostfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 17:55:44 -03:00
zhuyanlin
ec17cad69d arch:xtensa:include chip/irq.h instead of depend on chip config. 
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.

Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
 2021-08-05 10:08:48 +02:00
zhuyanlin
cec6aeb059 arch:xtensa:vector: fix typo error in level4_ventor 
Change-Id: I66cd3ff30e50e18ed718499aef609dd7aeb82dd3
 2021-08-04 20:16:41 -07:00
zhuyanlin
51d13df317 arch: xtensa: save current SP before overwrting in dispatch_c_isr. 
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.

Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
 2021-08-04 20:16:41 -07:00
zhuyanlin
4fc5b62ec3 arch:xtensa: use letter 'i' in inline assemble constraint instead of I 
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.

Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
 2021-08-04 18:23:40 +02:00
zhuyanlin
9a34705b80 arch:xtensa_testset: remove include arch/spinlock.h 
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.

Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
 2021-08-04 18:18:11 +02:00
zhuyanlin
355133f218 arch:xtensa: add new GNU toolchain for xtensa. 
Add support xcc,xclang GUN toolchin in xtensa,
ESP toolchain is default.

Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c
 2021-08-04 18:16:14 +02:00
Abdelatif Guettouche
238a96e7de arch/esp32_cpuint.c: Simplify up_disable/enable_irq. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
4f2f2ef9fb arch/xtensa: Get the cpu member out of the read only structure. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
239f0e257b arch/xtensa/esp32: Keep track to which CPU the interrupt was attached. 
This is used when dettaching.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
0ca5fb4edc arch/xtensa/esp32: When calling up_cpu_index no need to check if in SMP 
mode.  up_cpu_index already does that.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
3e44c347fd arch/xtensa/esp32_spi&i2c: Get the CPU index when attaching an 
interrupt.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Xiang Xiao
21b69cfd5d Replace all __attribute__((weak)) with weak_data/weak_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
007adc7736 Replace all __attribute__((section(x)) with locate_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
b3f9ffbe72 Replace all __attribute__((aligned(x)) with aligned_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Gustavo Henrique Nihei
a7a922611b xtensa/esp32: Enable the allocation of multiple SPI Flash partitions 
Currently the "esp32_spiflash_alloc_mtdpart" allocates a
statically-defined partition from "offset" and "size" set via
Kconfig.
This commit changes the function interface to receive those information
as arguments, enabling the creation of multiple MTD partitions with
different offsets and sizes.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-29 20:17:13 +02:00
Sara Souza
857414e95d xtensa/esp32: expose SPI2 as a char driver 2021-07-27 09:55:49 -07:00
Sara Souza
400d927011 xtensa/esp32s2: Disable wdt and wrap it. 2021-07-26 19:44:30 -07:00
Sara Souza
5baeb7430b xtensa/esp32: Wrap wdt deinitialization in a function 2021-07-26 19:44:30 -07:00
Gustavo Henrique Nihei
2d676f5e46 xtensa/esp32: Enable configuration of GPIO pad's drive strength 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-26 19:37:06 -07:00
jordi
f3af6edf93 Kconfig: add quotes in source to clean warnings from setconfig 
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"
 2021-07-23 02:32:19 -07:00
Abdelatif Guettouche
e85b119363 arch/: Clean what was made during context in distclean. 
Cleaning during `clean_context` had the issue of remaking everything
when `menuconfig` was issued.  That's because `menuconfig` has a
`clean_context` on its way.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-07-21 16:52:36 -03:00
Abdelatif Guettouche
315ba8c77f esp32_allocateheap.c: Remove the amount reserved to himem from the heap. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-07-21 08:58:18 -07:00
Alan C. Assis
011c938116 Remove xtensa_backtrace.S reference from esp32s2 as well 2021-07-20 19:30:09 -07:00
Alan C. Assis
d2eeeee262 Fix xtensa_btdump() to look at the exception frame 
Remove xtensa_backtrace_start() since it is not used anymore
 2021-07-20 19:30:09 -07:00
Gustavo Henrique Nihei
df2e890cfc xtensa/esp32: Implement MTDIOC_ERASESTATE for SPI Flash driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-17 09:00:41 -07:00
Xiang Xiao
98b5724b59 arch: Fix rtcb can't found error 
use the same condition check in declaration and reference

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
 2021-07-16 12:48:09 -03:00
Sara Souza
c7bf5c7a1d xtensa/esp32: Make UART TX DMA depends on EXPERIMENTAL and adds caveats regarding its use 2021-07-12 21:03:06 -07:00
Sara Souza
2abeba041d xtensa/esp32: Fixes termios issue. 2021-07-12 21:02:26 -07:00
Xiang Xiao
76cdd5c329 mm: Remove mm_heap_impl_s struct 
it's more simple to make mm_heap_s opaque outside of mm

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2
 2021-07-07 04:25:15 -07:00
Sara Souza
a5bf47b93e xtensa/esp32: Fixes issue with UART 2 2021-07-05 23:20:26 -05:00
Sara Souza
d67852da4b xtensa/esp32: Change default pins of UART2 2021-07-05 23:20:26 -05:00
Xiang Xiao
97216c220b mm: Support malloc_size function 
and rename malloc_usable_size to malloc_size

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
b1f711f790 mm: Move procfs_register_meminfo into common place 
to avoid the code duplication and ensure the consistent behaviour

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-03 09:39:32 -07:00
Sara Souza
b45ccad6a0 xtensa/esp32: Adds support for SERIAL_TXDMA. 2021-07-01 01:50:13 -05:00
Sara Souza
87fabb2bc7 xtensa/esp32: Support to select different clock source for RTC controller and close TODOs. 2021-06-30 21:27:27 -05:00
Abdelatif Guettouche
553f070357 arch/xtensa/esp32: Remove up_textheap_init function since it's not 
needed anymore.

Decouple the IRAM heap from the text allocator since that heap can
still be used as a generic pool of memory.

Implement the up_extraheaps_init function to initialize all of the
additional heaps.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-26 09:52:43 -05:00
Gustavo Henrique Nihei
db18a12844 xtensa/esp32: Move RTC WDT deinit after initial setup 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-06-25 10:58:39 -03:00
Gustavo Henrique Nihei
8c70e4f1c1 xtensa/esp32: Fix RTC watchdog timer deinit at startup 
Write protection must be disabled before performing changes to the WDT
registers. Furthermore, the routine was resetting the wrong field from
the RTC WDT register.
The RTC_CNTL_WDT_FLASHBOOT_MOD_EN field relates to Flash Boot Protection
and it is enabled by the 1st stage bootloader. The 2nd stage bootloader
takes care of disabling it.
Then the 2nd stage bootloader enables the RTC WDT for checking the
startup sequence of the application image.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-06-25 10:58:39 -03:00
Abdelatif Guettouche
55a210d305 arch/xtensa/esp32_textheap.c: When allocating text prioritize alloacting 
from the RTC heap.  If that's not available fall back to the IRAM heap.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
1e49f2929f arch/xtensa/src/esp32: Extract the IRAM region as a separate heap. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
1719e9df94 arch/xtensa/esp32: Add the RTC Slow memory as a separate heap. 
This memory region can be accessed by both I & D buses, so the heap can
be used for data storage and code execution.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00