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18113 Commits

Author SHA1 Message Date
Oleg
e95f23ef8b arch/arm/stm32f7/stm32_irq: Fix format strings 2021-08-31 16:56:55 +08:00
Alin Jerpelea
da92258333 arch: k210: remove extra license information 
the Apache license header uses a standard format and the extra information
should be removed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-31 08:20:18 +09:00
Xiang Xiao
b0c782255c libxx: Change CXX_LIBSUPCXX to LIBSUPCXX 
align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-28 17:14:48 -03:00
zhuyanlin
9ea7676731 arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS 
The name used in Tensilica support file core-isa.h for all vendors is
`XCHAL_NUM_INTLEVELS`.
Use a new name may be confused by newer porting xtensa arch.

Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de
 2021-08-28 21:51:45 +02:00
zhuyanlin
cd18d1f050 arch:riscv: remove arch atomic, use libc atomic when need 
It is more common for implement in libc/machine

Change-Id: I3da6c3db64adb78c05ddb26d3956817ac6ada93e
 2021-08-28 13:17:30 -03:00
Xiang Xiao
f0001574ed arch/armv8-m: Update per the latest architecture reference manual 
https://developer.arm.com/documentation/ddi0553/latest

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-27 11:39:27 +02:00
Abdelatif Guettouche
1385ea7673 arch/esp32: Properly handle GPIO interrupt in SMP. 
The PRO CPU and APP CPU have different peripherals for GPIO interrupts.
Each CPU needs to allocate an interrupt and attach it to its GPIO
peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-27 13:24:00 +09:00
chao.an
bcce3314e5 arch/arm/cortex-m: add up_backtrace support 
add up_backtrace support based on push/branch instruction

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 18:31:51 +08:00
chao.an
d5d6297ca1 arch/arm/assert: enhance the assert dump 
show the all tasks info including backtrace and registers

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 13:31:08 +08:00
chao.an
f14bd44001 arch/armv7: add up_backtrace support based on frame pointer 
This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory

This feature can not be used in THUMB2 mode if you are using GCC toolchain,
More details please refer:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-26 13:30:08 +08:00
Kapil Gupta
ec99e11f5e esp32/softap: Enable the WPA2 by default to ask user password 
Signed-off-by: Kapil Gupta <kapil.gupta@espressif.com>
Co-author: Alan Carvalho de Assis <alan.carvalho@espressif.com>
 2021-08-26 13:26:57 +08:00
ligd
f1aec38ffa arm: add ARM_HAVE_NEON to Kconfig 
Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-08-26 13:25:43 +08:00
Abdelatif Guettouche
fc594c5d25 esp32_irq.c: Extend the CPU interrupt/peripheral map to include the 
status of the interrupt (enabled/disabled).

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
810ed19b8f arch/xtensa/esp32_irq.c: Enable/disable interrupts using the Interrupt 
Matrix.

This allows manipulating interrupts from both CPUs.  Internal interrupts
however, still need to be disabled/enabled by each CPU.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
a7abd56448 arch/xtensa: Move the Xtensa specific part of interrupts to 
xtensa/include/irq.h

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
470799b0b3 arch/xtensa/esp32_irq: Remove the map/unmap IRQ functions they are used 
only inside this file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
04cd520293 arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
79cc12c034 arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq. 
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
237aebb7e1 arch/xtensa/esp32_cpuint.c: Refactor retrieving the intmap and register 
address of a peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
02c17c3169 arch/esp32: Simplify the interrupt allocation process. 
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
eefe7ebe5f xtensa/esp32_cpuint: export only one function to allocate a CPU 
interrupt.

That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.

All the drivers are also updated with this API change.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
dbdec45049 arch/xtensa/src/common: Use irq_spin APIs in modifyregXX 
Replace enter_critical_section with spin_lock_irqsave.
Replace leave_critical_section with spin_unlock_irqrestore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 23:32:40 +08:00
Abdelatif Guettouche
5ff703d5d0 arch/*_testset: Fix few typos. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-25 00:20:20 +08:00
Alin Jerpelea
07d528fd8d license: Ken Pettit: update licenses to Apache 
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-23 11:41:41 +08:00
chao.an
6cfb132232 arch/cortex-m: replace arm_switchcontext to c-style 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-22 14:44:01 +08:00
chao.an
68d6dbf86f arch/riscv/assert: enhance the assert dump 
enhance the assert dump to show the all tasks info including backtrace and registers

[    7.617000] [ EMERG] up_assert: Assertion failed at file:rv32im/riscv_exception.c line: 94 task: init
[    7.617000] [ EMERG] riscv_dumpstate: Call Trace:
[    7.617000] [  INFO] [BackTrace| 3|0]:  0x4202001e 0x42007cb4 0x42005782 0x42000fe2 0x403801e2 0x403800e2 0x4200bdd0 0x42009894
[    7.617000] [  INFO] [BackTrace| 3|1]:  0x4200a62e 0x42008e8a 0x4200841e 0x42008320 0x42005ad0 0x42001a56
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200bdd0
[    7.617000] [ EMERG] riscv_registerdump: A0:ffffffff A1:00000010 A2:3fc9a95c A3:00000031 A4:00000009 A5:00000002 A6:00000001 A7:00000074
...
...
[    7.617000] [ EMERG] riscv_showtasks: Tasks status:
[    7.617000] [ EMERG] riscv_taskdump: Idle Task: PID=0
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=596 of 976
[    7.617000] [  INFO] [BackTrace| 0|0]:  0x4200787e 0x3fc94ff0
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200787e
[    7.617000] [ EMERG] riscv_registerdump: A0:00000032 A1:3c1008fa A2:3fc94fa8 A3:00000000 A4:00000101 A5:00000032 A6:00000001 A7:00000074
...
[    7.617000] [ EMERG] riscv_taskdump:
[    7.617000] [ EMERG] riscv_taskdump: hpwork: PID=1
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=292 of 2016
[    7.617000] [  INFO] [BackTrace| 1|0]:  0x420082a6 0x4200328c 0x42001ab4 0x42001a42
[    7.617000] [ EMERG] riscv_registerdump: EPC:420082a6
[    7.617000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc98718 A2:3fc8307c A3:00000002 A4:00000000 A5:00000000 A6:00000000 A7:00000000
...

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:58:21 +08:00
chao.an
333191becd riscv/backtrace: add up_backtrace support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:56:34 +08:00
Abdelatif Guettouche
2925d4956b xtensa/esp32: Use up_cpu_index instead of this_cpu. 
this_cpu requires sched.h to be included.
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5d626f7267 xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs 
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
56a7f3b651 arch/xtensa/esp32: Update the drivers regarding the API change in IRQ 
handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5be9f24fe5 arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted. 
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
97dca8fe10 arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and 
irq.c

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
633cdf8e27 arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts. 
This map also keeps track of the CPU that attached the IRQ.  This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Sara Souza
e092c457e6 xtensa/lx7: Fix the CROSSDEV variable 2021-08-20 16:48:20 +02:00
Xiang Xiao
af72376773 fs: Remove magic field from partition_info_s 
since it is wrong and impossible to return file
system magic number from the block or mtd layer.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 09:19:52 -03:00
Antti Vähälummukka
6eb73ced51 arch/risc-v/src/mpfs: Add CorePWM driver 
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA

This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
 2021-08-20 08:56:30 -03:00
Xiang Xiao
4b41579ccf arch/armv8-m: Add SAU support 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 10:22:43 +09:00
raiden00pl
78962165d8 arch/stm32: add 3-phase Hall effect sensor lower half 2021-08-19 08:19:38 -07:00
chao.an
1060953567 sched/backtrace: add sched_backtrace support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 01:30:50 -07:00
chao.an
0a8d951837 arch/arm: correct the frame pointer register declare 
In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 01:26:07 -07:00
Abdelatif Guettouche
cd0f64d779 xtensa/irq.h: Add a macro to convert to an IRQ from a peripheral ID. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-18 10:49:58 -03:00
raiden00pl
532ec126e9 stm32/stm32_serial.c fix compile error when CONFIG_STM32_SERIALBRK_BSDCOMPAT=y. 
Fix for https://github.com/apache/incubator-nuttx/issues/4353
 2021-08-18 04:43:32 -07:00
Abdelatif Guettouche
a220766d57 xtensa.h: Remove unused function prototype. 
ESP32 uses a different function to start the app CPU and no other xtensa
CPU uses this __cpu1_start function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-18 04:41:40 -07:00
chao.an
e37d8da074 riscv/common: add CURRENT_REGS declare in RV32 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-18 04:40:38 -07:00
Juha Niskanen
e02e1c25f6 arch/arm/src/stm32l4/Kconfig: add new STM32L4+ chip types 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Change-Id: I74050913643db23b4d03abaf516989ff3cdac142
 2021-08-17 06:27:18 -07:00
Alin Jerpelea
4b20cf30c0 arch: misoc: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-16 07:11:32 -07:00
Alin Jerpelea
351091ed75 author: Pierre-noel Bouteville: update licenses to Apache 
Gregory Nutt has submitted the SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-16 07:11:32 -07:00
Xiang Xiao
71269811ca mtd: Implement BIOC_PARTINFO for all drivers 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-16 10:08:26 -03:00
Virus.V
5a1de89370 riscv/bl602: Fix that AP cannot be start when STA have been started. 2021-08-16 02:06:59 -07:00
Xiang Xiao
f63d1cfbbb arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-15 10:50:52 +02:00
Xiang Xiao
fad0c3b38b arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-14 11:41:59 -07:00
Xiang Xiao
33666832c5 arch/arm: Add NVIC_AIRCR_VECTKEY macro to avoid the hard code value 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-14 11:41:59 -07:00
Abdelatif Guettouche
5b350f3a0f arch/*_reprioritizertr.c: Fix typos in comments. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-14 11:19:34 -07:00
Gustavo Henrique Nihei
1dfcc6ab49 xtensa/esp32: Enable boot from Espressif's port of MCUboot 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-08-13 08:44:20 -03:00
zhuyanlin
1a1b1cc2b4 arch:xtensa: replace include file from src/chip_xxx to chip.h 
Use chip.h as a standard include file, replace chip_xxx in src dir
 2021-08-12 16:18:35 +02:00
zhuyanlin
30a2338e92 arch:esp: create chip.h header for chip src code. 
Create chip.h header for esp src code.
 2021-08-12 16:18:35 +02:00
zhuyanlin
6d592256fb arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h 
Those header contain syntax not be recognize by gnu assembler.
 2021-08-12 16:18:35 +02:00
Alexander Vasiljev
4229099944 arch/arm/stm32h7: dma and serial: add TRBUFF flag. It is obligatory for uart. 2021-08-12 08:07:18 -03:00
Xiang Xiao
6b6c11f0ad mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-12 08:01:29 -03:00
Xiang Xiao
d1687418db mtd: Remove the empty MTDIOC_XIPBASE implmentation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-11 09:50:51 -03:00
zhuyanlin
e333733053 xtensa:coproc: fix XTENSA_CP_ALLSET error in some case 
Consider follow coprocessor configuration case:

\#define XCHAL_CP_NUM                    1       /* number of coprocessors */
\#define XCHAL_CP_MAX                    2       /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK                   0x02    /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK              0x00    /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME                  "AudioEngineLX"
\#define XCHAL_CP1_IDENT                 AudioEngineLX
\#define XCHAL_CP1_SA_SIZE               208     /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN              8       /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX       1       /* coprocessor ID (0..7) */

In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.

Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
 2021-08-10 19:44:55 -07:00
Abdelatif Guettouche
054e284785 *_cpustart.c: Fix typos in function description. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-11 11:06:27 +09:00
Fotis Panagiotopoulos
5b7ff03f40 lpc17_40: Fixed I2C port sanity check. 2021-08-10 09:04:33 -07:00
raiden00pl
2b3106fb47 Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
51b24c4bad stm32/qenco: add support for QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
092a0c8453 stm32/qenco: add an option to disable encoder timer extension from 16-bit to 32-bit 
Previous implementation has always expanded the width of the timer to 32-bit.
This feature is not always needed and should be configurable from Kconfig.
 2021-08-10 11:18:40 -03:00
raiden00pl
b0c9a6133e stm32/qenco: fix TIM2 width for STM32F3 which is 32-bit not 16-bit 
STM32F3 has timers of the same length as in STM32F4.
 2021-08-10 11:18:40 -03:00
raiden00pl
3dd385ac0c stm32/qenco: add support for STM32G4 
This required generalization of RCC definitions that are not compatible with previous chips
 2021-08-10 11:18:40 -03:00
raiden00pl
21f59c874f stm32/qenco: fix compilation for STM32F1. GTIM_CCER_CCxNP bits are not present in F1 2021-08-10 11:18:40 -03:00
Sara Souza
af6c311fd1 risc-v/esp32-c3: Complete the support for RWDT 2021-08-10 11:17:15 -03:00
Sara Souza
61ab4f9f14 xtensa/esp32: Fix the type of enum passed between functions in esp32_rtc_clk 2021-08-10 11:15:51 -03:00
Sara Souza
67d29e7537 xtensa/esp32: initialize RTC in case PM or RTC configs are not set, but RWDT is. 2021-08-10 11:15:51 -03:00
zhuyanlin
5820972727 arch:xtensa: add arch stdarg.h include file for xtensa 
Add arch/include/stdarg.h for xtensa.

Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56
 2021-08-09 17:58:25 -03:00
Xiang Xiao
776458143c fs/hostfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 17:55:44 -03:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition 
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-07 09:20:10 -03:00
Daniel P. Carvalho
a7be1c9a2e stm32_pmw: fix pwm_stop() function to enable multiple PWM start and stop. 2021-08-05 14:48:44 -03:00
Michal Lenc
a3986eeba3 arch/arm/src/imxrt/imxrt_flexpwm.c: Set LDOK bits after all channels are set 
This commit changes the FLexPWM driver for iMXRT MCU so that LDOK bits in
Master Control Register are set at once after all channels are configured.
Setting LDOK bit enables the driver to load prescaler, modulus and PWM
values of corresponging submodule and start PWM output. Setting all bits
at once instead of doing it separately can help avoiding the channels to
be out of sync with each other.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-08-05 09:57:49 -07:00
zhuyanlin
ec17cad69d arch:xtensa:include chip/irq.h instead of depend on chip config. 
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.

Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
 2021-08-05 10:08:48 +02:00
zhuyanlin
cec6aeb059 arch:xtensa:vector: fix typo error in level4_ventor 
Change-Id: I66cd3ff30e50e18ed718499aef609dd7aeb82dd3
 2021-08-04 20:16:41 -07:00
zhuyanlin
51d13df317 arch: xtensa: save current SP before overwrting in dispatch_c_isr. 
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.

Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
 2021-08-04 20:16:41 -07:00
Daniel P. Carvalho
2593089f84 stm32_dac: add support for DAC3 2021-08-04 20:22:58 +02:00
zhuyanlin
4fc5b62ec3 arch:xtensa: use letter 'i' in inline assemble constraint instead of I 
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.

Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
 2021-08-04 18:23:40 +02:00
zhuyanlin
9a34705b80 arch:xtensa_testset: remove include arch/spinlock.h 
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.

Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
 2021-08-04 18:18:11 +02:00
zhuyanlin
355133f218 arch:xtensa: add new GNU toolchain for xtensa. 
Add support xcc,xclang GUN toolchin in xtensa,
ESP toolchain is default.

Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c
 2021-08-04 18:16:14 +02:00
Xiang Xiao
6a396eb224 Fix the printf warning after off_t change 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Id46daa2ee690a73d3187b479f0e7ab0e2e361764
 2021-08-04 06:48:30 -07:00
Abdelatif Guettouche
238a96e7de arch/esp32_cpuint.c: Simplify up_disable/enable_irq. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
4f2f2ef9fb arch/xtensa: Get the cpu member out of the read only structure. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
239f0e257b arch/xtensa/esp32: Keep track to which CPU the interrupt was attached. 
This is used when dettaching.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
0ca5fb4edc arch/xtensa/esp32: When calling up_cpu_index no need to check if in SMP 
mode.  up_cpu_index already does that.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
3e44c347fd arch/xtensa/esp32_spi&i2c: Get the CPU index when attaching an 
interrupt.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
licheng
431df45e97 EXC_SECURE and SECURE_STACK just can clear at TRUSTZONE_NONSECURE 2021-08-02 23:20:34 -07:00
Alexander Lunev
95abf562f4 boards: added a basic support for chipKIT Wi-FIRE board; 
added Sourcery CodeBench Lite for MIPS ELF Toolchain option;
corrected inaccuracies in Photon board and EMW3162 board README.txt files.
 2021-08-01 08:45:02 -07:00
buyuer
ae3709819c Use exit func iml host_abort. 
When use poweroff command,host_abort will be called,but may be make __stack_chk_fail irq, and host_abort be called in PANIC(), so bring infinite loop, in turn it can not exit SIM.

Signed-off-by: buyuer <dingddding@163.com>
 2021-07-31 08:02:10 -07:00
Xiang Xiao
5d1a444812 Replace __attribute__ ((unused)) with unused_code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
69df58c2e8 Replace __attribute__((no_instrument_function)) with noinstrument_function; 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
7bcd29dae0 Replace __attribute__((naked, no_instrument_function)) with naked_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
919f8a9a72 Define __ramfunc__ to "locate_code(".ramfunc") farcall_function noinline_function" 
instead of "__attribute__ ((section(".ramfunc"),long_call,noinline))"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
21b69cfd5d Replace all __attribute__((weak)) with weak_data/weak_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
007adc7736 Replace all __attribute__((section(x)) with locate_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
b3f9ffbe72 Replace all __attribute__((aligned(x)) with aligned_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00