Enable with ./tools/configure.sh -l esp32-devkitc:dac
DAC channel 0 = GPIO 25
DAC channel 1 = GPIO 26
default path: /dev/dac0
Resolution 8 bits = values 0~255
Voltage: 0~Vref
The reference voltage 'Vref' here is input from the pin VDD3P3_RTC
which ideally equals to the power supply VDD (3.3V).
This adds support for creating an early frame buffer and primatives for
writing to this frame buffer as a console. This does require the font
infrastructure as well as multiboot2.
Additionally this can now be used with a UEFI bootloader long as it
boots NuttX via Multiboot2. There does seem to be a PCI interrupt
issue when running in UEFI mode.
I was able to boot my laptop using this and see PCI devices enumerate.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
x86_64: Add conditionals around the multiboot framebuffer
Squashed commits:
1. Porting prior PCI work in place of jailhouse code
At this point the PCI enumeration works for x86_64 including over
pci-pci bridges.
Running QEMU with this configuration we see the bridge and the
device on the bridge. It also detected the qemu test device
qemu-system-x86_64 \
-cpu host,+pcid,+x2apic,+tsc-deadline,+xsave,+rdrand \
--enable-kvm -smp 1 -m 2G -cdrom boot.iso --nographic -no-reboot \
-device pci-testdev \
-device pci-bridge,id=bridge0,chassis_nr=2 \
-device e1000,bus=bridge0,addr=0x3
qemu_pci_init: Initializing PCI Bus
pci_probe_device: [00:00.0] Found 8086:1237, class/revision 06000002
pci_probe_device: [00:01.1] Found 8086:7010, class/revision 01018000
pci_probe_device: [00:01.2] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.3] Found 8086:7113, class/revision 06800003
pci_probe_device: [00:01.4] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.5] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.6] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.7] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:02.0] Found 1234:1111, class/revision 03000002
pci_probe_device: [00:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:04.0] Found 1b36:0005, class/revision 00ff0000
pci_probe_device: [00:04.0] Probing
pci_check_pci_bridge: [00:05.0] Found Bridge
pci_probe_device: [01:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:05.0] Found 1b36:0001, class/revision 06040000
2. Remove unused CONFIG_PCI_MAX_BDF option
3. Add a workaround for Jailhouse pci scanning
4. Extend BAR parsing and handle PIO and MMIO for pci-testdev
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
5. PCI: Add initial support for QEMU 'edu' test device
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
6. Bring up PCI later in boot process
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
7. Add ISR and DMA support to QEMU edu test pci device
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
8. Fix bad function prototype definition in qemu_edu
9. intel64: Add a pci test configuration and instructions
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
10. PCI: Fix issue in identification of 64bit bar
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
- spi/slave.h: revise comments in pulic types section
- doc/sim.rst: minor formatting, add ways to escape cu
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
USART peripheral can work in SPI mode as well. This commit adds support
for such functionality. Only 1 slave device is supported by the
peripheral therefore board level does not have to ensure correct CS
setup.
The usage of the peripheral is the same as with other SPI drivers.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This slightly revised the USB host documentation and fixed typos
encountered in the document and some source files.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Changes:
- Documentation/platforms/risc-v/k230 revised for both modes
- arch/risc-v/include/k230/irq.h add S-mode IRQs
- under arch/risc-v/src/k230 folder:
- Make.defs drop use of k230_exception_m.S
- hardware/k230_clint.h add S-mode defs, revised freq
- k230_head.S unified flat/kernel mode support
- k230_irq.c add S-mode support with debug dump
- k230_mm_init.c revised for K230 S-mode
- k230_start.c revised for flat/s-mode,
- arch/risc-v/src/k230/k230_timerisr.c unified flat/s-mode support.
- under boards/risc-v/k230/canmv230 folder:
- configs/nsh/defconfig fix RAM size
- include/board_memorymap.h cleanup for S-mode
- src/.gitignore ignore romfs_boot.c
- src/Makefile add romfs support
Renames:
- under boards/risc-v/k230/canmv230/src/ folder:
- canmv_init.c from k230_appinit.c making room for more k230 devices
Dropped:
- under arch/risc-v/src/k230/
- k230_exception_m.S as hybrid mode not ready yet.
New files in boards/riscv/k230/canmv230:
- configs/knsh/defconfig S-mode config
- scripts/ld-kernel.script S-mode linker script
- src/romfs.h User space ROMFS defs needed in S-mode
- src/romfs_stub.c Stub ROMFS image
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.
Major changes:
- boards/Kconfig: add new BOARD_K230_CANMV
- arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
select MMIO access width
New additions:
- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/: k230 SoC sources
- boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc
Note that only FLAT build works for canmv230 now.
This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.
Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.
The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.
So by design this change should be safe but RiscV ports should be checked.
"ostest" verification has been done for:
- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64
configuration generation and manual check of derived RV_MMIO_BITS has been
done for:
- star64/nsh
- arty_a7/nsh
- bl602evb/nsh
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This PR adds support for PINE64 Ox64 64-bit RISC-V SBC, based on Bouffalo Lab BL808 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Star64 JH7110. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
### Modified Files
`boards/Kconfig`: Added Ox64 board
### New Files in boards/risc-v/bl808/ox64
`src/bl808_appinit.c`: Startup Code
`include/board.h`: Ox64 Definitions
`include/board_memorymap.h`: Memory Map
`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script
`src/.gitignore`: Ignore the tmp filesystem
`scripts/ld.script`: Linker Script
`scripts/Make.defs`: Ox64 Makefile
`src/Makefile`: Ox64 Makefile
`Kconfig`: Ox64 Config
`configs/nsh/defconfig`: Build Config for `ox64:nsh`
### Updated Documentation
`platforms/risc-v/bl808/index.rst`: New page for Bouffalo Lab BL808 SoC
`platforms/risc-v/bl808/boards/ox64/index.rst`: Building and booting NuttX for Ox64
`platforms/risc-v/jh7110/boards/star64/index.rst`: Fix typo
ignore known warnings:
/home/raiden00/git/RTOS/nuttx/nuttx/Documentation/reference/os/netdev.rst:61: WARNING: Duplicate C declaration, also defined at reference/os/netdev:39.
Declaration is '.. c:struct:: net_driver_s'.
/home/raiden00/git/RTOS/nuttx/nuttx/Documentation/reference/user/07_signals.rst:180: WARNING: Duplicate C declaration, also defined at reference/user/structures:112.
Declaration is '.. c:struct:: sigaction'.
There are ICs available on the market that integrate various power inverter
features. The driver for such a device must be tightly coupled to a FOC device
as using it as a separate device doesn't make sense.
Summary:
- Upgraded to xpack-riscv-none-elf-gcc-12.3.0-2 to resolve symbol recognition
issues in riscv-none-elf-gdb, as reported in
https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/issues/22.
Impact:
- Expected to enhance toolchain stability with no negative side effects.
Testing:
- Verified with rv-virt:netnsh and rv-virt:netnsh64 configurations
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Copyright notice and author contact/information should not be included
in file header anymore. Only standard Apache 2.0 licensing information
should be used.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Documentation/legacy_README.md:675: WARNING: duplicate label introduction/resources:installation, other instance in Documentation/introduction/resources.rst
testing badges
Converted legacy readme from .md to .rst
Revert "Converted legacy readme from .md to .rst"
This reverts commit e33fef7a5aaa5dd377f87b90a667a2704b9fb834.
- migrated /README are removed from /boards
- there are a lot of READMEs that should be further converted to rst.
At the moment they are moved to Documentation/platforms and included in rst files
Update the gcc compiler to 10.3-2021.10 to be able to compile the latest NuttX version
Fix for error:
arm-none-eabi-g++: error: unrecognized command line option '-std=gnu++20';
did you mean '-std=gnu++2a'?
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Our releases contain links to github PR and lots of text so we
are splitting the release notes to individual files
This change should
- improve readability
- reduce the ReleaseNotes file for each release.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
External JLink is required to program the board, so the console via RTT
is available anyway. It is much more convenient to use than soldering the
P4 connector and working with an external UART converter.
We support search directory structure as follows:
Current directory
stm32/configs/common
stm32/common/configs
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
To solve the issue of carrying object files from previous builds,
Matias changed the archiving process to re-archive libapps.a on every compilation,
if libapps.a carries more object files, incremental compilation will waste too
many time in re-archiving, compared with the previous implement, this is a degradation
of the build system. Referring to mature engineering projects such as cmake, if there
is configuration or source file changed, the best solution should be to reconfigure
the environment.
Revert this PR to ensure the compilation speed during incremental compilation.
| commit 34b34e2d45 (tag: nuttx-20200914-172150)
| Author: Matias N <matias@protobits.dev>
| Date: Fri Sep 11 22:31:38 2020 -0300
|
| Fix: ensure archive files do not carry object files from prior builds
|
| In some cases, when NuttX configuration changes and this makes the
| object list used to build one of the .a libraries change as well,
| since the command used to build it is "ar crs" and this simply appends
| the list of object files, the library could still include object
| files from prior builds. This commit modifies the ARCHIVE macro to
| erase the .a file if it already exists.
|
| Since in some cases this behavior was actually expected (object
| files from a subdirectory were appended to a library created one
| level above) I added a ARCHIVE_ADD which works as ARCHIVE did.
|
| This change should greatly improve behavior of building after
| configuration changes.
Testing:
sim:nsh
-------------------------------
| Patched | Current
-------------------------------
|$ time make | $ time make
|real 0m1.270s | real 0m1.728s
|user 0m0.971s | user 0m1.276s
|sys 0m0.363s | sys 0m0.530s
-------------------------------
Private project (20+ 3rd library needs archive to libapps.a)
-------------------------------
| Patched | Current
-------------------------------
|$ time make | $ time make
|real 0m21.181s | real 0m39.721s
|user 0m14.638s | user 0m24.837s
|sys 0m6.919s | sys 0m14.394s
-------------------------------
Signed-off-by: chao an <anchao@xiaomi.com>
The board-level GPIO support is different from the already existing
button and LEDC support because it enable us to register the GPIO
pins as devices in `/dev/gpioX`. Some applications are able to use
this interface to read and write the GPIO pins.
Documentation was added regarding its usage. Please check
`Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst`
According to `Documentation/guides/gdbwithpython.rst` and GDB's
documentation, the `-ix` option "Execute commands from file `file`
before loading the inferior (but after loading gdbinit files)",
being the correct way of loading it to GDB.
This PR adds support for PINE64 Star64 64-bit RISC-V SBC, based on StarFive JH7110 SoC. Most of the code is derived from NuttX for QEMU RISC-V (Kernel Mode). [The source files are explained in the articles here](https://github.com/lupyuen/nuttx-star64)
Modified Files:
boards/Kconfig: Added Star64 board
New Files in boards/risc-v/jh7110/star64:
src/jh7110_appinit.c: Startup Code
include/board.h: Star64 Definitions
include/board_memorymap.h: Memory Map
src/etc/init.d/rc.sysinit, rcS: Startup Script
src/.gitignore: Ignore the tmp filesystem
scripts/ld.script: Linker Script
scripts/Make.defs: Star64 Makefile
src/Makefile: Star64 Makefile
Kconfig: Star64 Config
configs/nsh/defconfig: NSH Build Config
Updated Documentation:
introduction/detailed_support.rst: Added StarFive JH7110 SoC and Star64 SBC
platforms/risc-v/jh7110/index.rst: New page for StarFive JH7110 SoC
platforms/risc-v/jh7110/boards/star64/index.rst: Building and booting NuttX for Star64
Add documentation referring to sim:alsa defconfig, about how to
mount host system files in the simulator using `hostfs` and
playing them using the ALSA adapter.
support to control the opening or closing of the specified channel through the syslogmask command at runtime
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
use PTHREAD_CLEANUP_STACKSIZE to enable or disable interfaces pthread_cleanup_push() and pthread_cleanup_pop().
reasons:(1)same as TLS_TASK_NELEM (2)it is no need to use two variables
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
* Documentation/guides/cortexmhardfaults.rst:
New. Migrated from [1] with conversion to reStructuredText,
minor typo fixes, and a link to a Narkive archive of the
original quoted question.
* Documentation/guides/index.rst:
Add above to TOC.
[1] https://cwiki.apache.org/confluence/display/NUTTX/Analyzing+Cortex-M+Hardfaults
