This commit exends systimer options for nRF52 arch. It is possible
to use ARM SysTick either for tickless or non-tickless mode. Also,
it is possible to use the RTC peripheral for tickless mode. This
also re-enables support for WFI/WFE sleep if RTC is used, since
this counter continues to run in this mode (in contrast to SysTick).
Summary:
- ARCH_GLOBAL_IRQDISABLE was initially introduced for LC823450 SMP
- At that time, i.MX6 (quad Cortex-A9) did not use this config
- However, this option is now used for all CPUs which support SMP
- So it's good timing for refactoring the code
Impact:
- Should have no impact because the logic is the same for SMP
Testing:
- Tested with board: spresense:smp, spresense:wifi_smp
- Tested with qemu: esp32-core:smp, maix-bit:smp, sabre-6quad:smp
- Build only: lc823450-xgevk:rndis, sam4cmp-db:nsh
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
- Add new functions of GNSS
- Support the lower PWM frequency
- Add CONFIG_CPUFREQ_RELEASE_LOCK
- Add high speed ADC support
- Add HPADC input gain configuration
- Add eMMC device
- Frame buffer support
- Fix SD/GNSS/sensor drivers not worked
- Build errors
- Fix nxstyle issues
The QuickFeather board added as an initial target.
These featrues are minimally implemented:
* Clock Configuration -- All clocking registers are defined and
configuration is used to setup the HSO, M4 Core, and M4 Perif
clocks. Additionally some clock debugging is stubbed for
bringing out clock paths to IO pins.
* UART -- The lowputc as well as the serial driver is implemnted
for the single UART device. Currently the configuration is
hard coded, but uses the proper interfaces to later fill in.
* SysTick -- The system tick timer is implemented and clocking
properly. Tickless mode is not yet implemented.
* Interrupts -- The interrupt system is implemented and verified
using the UART and SysTick systems.
* GPIO -- GPIO and IOMUX systems are defined and implemented.
This is verified using the UART as well as the Arch LED
system. The GPIO interupt system is stubbed out but not
implemented.
* Arch LEDS -- The blue LED as part of the RGB LED is configured
and attached to the Arch LED system. This indicates the device
coming online as well as when a hardfault is triggered.
Applications and Testing:
* There is a nsh configuration implemented that includes debug
features as well as the ostest, getprime, and mem test.
All of these have been run and verified.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Add support for the STM32G474 family of microcontrollers and the
B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.
This is a major pull request as it adds support for an entirely
new family of STM32. This support is implemented in
arch/arm/src/stm32 and shares implementation with other STM32
families supported by that code, such as the 'L15xx, 'F10xx,
'F20xx, 'F3xxx, and 'F4xxx.
arch/arm/Kconfig:
arch/arm/include/stm32/chip.h:
arch/arm/include/stm32/irq.h:
arch/arm/src/stm32/Kconfig:
arch/arm/src/stm32/hardware/stm32_adc.h:
arch/arm/src/stm32/hardware/stm32_adc_v2.h:
arch/arm/src/stm32/hardware/stm32_dma.h:
arch/arm/src/stm32/hardware/stm32_dma_v1.h:
arch/arm/src/stm32/hardware/stm32_flash.h:
arch/arm/src/stm32/hardware/stm32_i2c.h:
arch/arm/src/stm32/hardware/stm32_i2c_v2.h:
arch/arm/src/stm32/hardware/stm32_memorymap.h:
arch/arm/src/stm32/hardware/stm32_pinmap.h:
arch/arm/src/stm32/hardware/stm32_tim.h:
arch/arm/src/stm32/stm32_allocateheap.c:
arch/arm/src/stm32/stm32_dma.c:
arch/arm/src/stm32/stm32_dma_v1.c:
arch/arm/src/stm32/stm32_dumpgpio.c:
arch/arm/src/stm32/stm32_gpio.c:
arch/arm/src/stm32/stm32_gpio.h:
arch/arm/src/stm32/stm32_lowputc.c:
arch/arm/src/stm32/stm32_rcc.c:
arch/arm/src/stm32/stm32_rcc.h:
arch/arm/src/stm32/stm32_serial.c:
arch/arm/src/stm32/stm32_syscfg.h:
arch/arm/src/stm32/stm32_uart.h:
* Add architectural support to existing NuttX files. This
makes the STM32G474 family parts accessible to the system.
With big thanks for detailed code review:
David Sidrane (davids5)
Mateusz Szafoni (raiden00)
Abdelatif Guettouche (Ouss4)
1. Add dsp extension; float point based on hardware and software.
2. Delete folder "iar"
3. Add tool chain for cortex-M23 and cortex-M35p
Signed-off-by: qiaowei <qiaowei@xiaomi.com>
Change-Id: I5bfc78abb025adb0ad4fae37e2b444915f477fe7
Spresense smp
* arch: arm: Add ARCH_GLOBAL_IRQDISABLE to ARCH_CHIP_CXD56XX in Kconfig
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Make fpuconfg() public in cxd56_start.c
NOTE: fpuconfig() is called in both cxd56_start.c and cxd56_cpustart.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Add support for SMP
NOTE: To run cxd56xx in SMP mode, new boot loader which will be
released later must be used.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Add irq routing for SMP in cxd56_irq.c
NOTE: In cxd56xx, each external interrupt controller can be
accessed from a local APP_DSP (Cortex-M4F) only. This commit
supports IRQ routing for SMP by calling up_send_irqreq() in
both up_enable_irq() and up_disable_irq().
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* boards: spresense: Add smp configuration
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Move boards to boards folder
* boards: rename configs folder to boards
This is the proposed layout after the change:
boards: - folder containing board folders
<board>: - name of each board
drivers: - extra drivers specific for platform
include: - header files for the boars
scripts: - extra scripts specific for platform
src: - board specific code
tools: - extra tools specific for platform
<config>: - board specific configuration(s)
Note:
<xxx> names are dependent on platform
This is a logical change to aim to the arch layout but this is a
huge change it should be done in several steps to lower the risk.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Kconfig: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Makefile: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Makefile.*: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Make.defs: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .sh: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .mk: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .c & .h: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .bat: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Add support for LPC40xx family chips
* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit. These configurations are still something of a work in progress. In particular, the LCD functionality is untested.
* First pass rename in *.c and *.h files.
* Renamed LPC17XX to LPC17XX_40XX in config files
* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files
* Replaced LPC17xx with LPC17xx/LPC40xx in .h files
* Updated some documentation
* Working on moving directories
* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx
* Renamed LPC17_* constants / configuration options to LPC17_40_*
* Updated chip family name defines
* Renamed some chip-specific files
* Updated references to renamed files
* Updated references to lpc17_ to lpc17_40_
* Renamed source files from lpc17_* to lpc17_40_*
* Clean up white space
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm: Rename include/stm32f0l0 and src/stm32f0l0 to stm32f0l0g0.
Change all occurrences of lower-case stm32f0l0 to stm32f0l0g0.
Change all occurrences of upper-case STM32F0L0 to STM32F0L0G0.
libs/libc/pthread/pthread_spinlock.c: Resolve several TODO issues by accessing up_testset() via the boardctl() interface rather than attempting to call it directly.
configs/boardctl.c, include/sys/boardctl.h: Add access to architecture-specific up_testset() via boardctl().
arch/Kconfig's, sched/Kconfig, and include/nuttx/spinlock.h: Spinlocks are not available unless the architecture supports the up_testset() operation.
arch/arm/src/tiva/hardware: Add CC13xx SMPH and AUX SMPH header files. Still need DDI0 OSC header file for CC13x0 compilation.
arch/arm/src/tiva/cc13xx: A few changes toward getting the launchxl-cc1310/nsh configuration to build
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Many small changes related to coding style.
Author: Petro Karashchenko <petro.karashchenko@gmail.com>
configs/beaglebone-black: Adds initial support for the BeagleBone Black board.
arch/arm/src/am335x: Adds initial support for the TI AM355x family.
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
arch/arm/src/stm32f0l0: Some fixes for a clean build. Still have a problem with lots of error messages coming from kconfig-mconf, but the configuation looks fine. Sometimes kconfig errors are difficult to spot. I would appreciate it anyone can spot the issue.
arch/arm/src/stm32f0l0/hardware: Rename the chip directory to hardware. This will hopefully eliminate some problems that I have seen with the chip include paths not being unique in more complex configuartions.
configs/nucleo-f072rb, configs/nucleo-f091rc, configs/stm32f051-discovery, and configs/stm32f072-discovery: Update for all of the naming changes made in arch/arm/src/stm32f0l0
arch/arm/include/stm32f0l0: Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0. Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic.
arch/arm/src/stm32f0l0: Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0. Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic.
arch/arm/src/tiva/hardwar: Move LM3S and LM4F include files to hardware/lm/ sub-directory. Move all TM4C header files files to hardware/tm4c/ sub-directory.
arch/arm: Add basic configuration/build support for CC13xx parts. Conditioned on EXPERIMENTAL.
This update is required to be serialized to the instruction stream meaning that after this update completes, it takes effect immediately and no exceptions of lower priority than the new boosted priority can pre-empt execution. Because of this erratum, the priority boosting does not take place immediately, allowing the instruction after the MSR to be interrupted by an exception of lower priority than the new boosted priority. This effect is only limited to the next instruction. Subsequent instructions are guaranteed to see the new boosted priority.
This was raised in Bitbucket issue 113 from Vadzim Dambrouski.
