nuttx/arch/arm/Kconfig

#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_ARM
comment "ARM Options"

choice
	prompt "ARM MCU selection"
	default ARCH_CHIP_STM32

config ARCH_CHIP_A1X
	bool "Allwinner A1X"
	select ARCH_CORTEXA8
	select ARCH_HAVE_FPU
	select ARCH_HAVE_IRQPRIO
	select ARCH_HAVE_LOWVECTORS
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_SDRAM
	select BOOT_RUNFROMSDRAM
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	---help---
		Allwinner A1X family: A10, A10S (A12), A13 (ARM Cortex-A8)

config ARCH_CHIP_BCM2708
	bool "Broadcom BCM2708"
	select ARCH_ARM1176JZ
	select ARCH_HAVE_LOWVECTORS
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	select ARCH_HAVE_TICKLESS

config ARCH_CHIP_C5471
	bool "TMS320 C5471"
	select ARCH_ARM7TDMI
	select ARCH_HAVE_LOWVECTORS
	select OTHER_UART_SERIALDRIVER
	---help---
		TI TMS320 C5471, A180, or DA180 (ARM7TDMI)

config ARCH_CHIP_DM320
	bool "TMS320 DM320"
	select ARCH_ARM926EJS
	select ARCH_HAVE_LOWVECTORS
	---help---
		TI DMS320 DM320 (ARM926EJS)

config ARCH_CHIP_EFM32
	bool "Energy Micro"
	select ARCH_HAVE_SPI_BITORDER
	select ARCH_HAVE_FETCHADD
	---help---
		Energy Micro EFM32 microcontrollers (ARM Cortex-M).

config ARCH_CHIP_IMX1
	bool "NXP/Freescale iMX.1"
	select ARCH_ARM920T
	select ARCH_HAVE_HEAP2
	select ARCH_HAVE_LOWVECTORS
	---help---
		Freescale iMX.1 architectures (ARM920T)

config ARCH_CHIP_IMX6
	bool "NXP/Freescale iMX.6"
	select ARCH_CORTEXA9
	select ARMV7A_HAVE_L2CC_PL310
	select ARCH_HAVE_FPU
	select ARCH_HAVE_TRUSTZONE
	select ARCH_HAVE_LOWVECTORS
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_SDRAM
	select BOOT_RUNFROMSDRAM
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	---help---
		Freescale iMX.6 architectures (Cortex-A9)

config ARCH_CHIP_IMXRT
	bool "NXP/Freescale iMX.RT"
	select ARCH_CORTEXM7
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_RAMFUNCS
	select ARCH_HAVE_TICKLESS
	select ARCH_HAVE_I2CRESET
	select ARCH_HAVE_SPI_CS_CONTROL
	select ARM_HAVE_MPU_UNIFIED
	select ARMV7M_HAVE_STACKCHECK
	---help---
		NXP i.MX RT (ARM Cortex-M7) architectures

config ARCH_CHIP_KINETIS
	bool "NXP/Freescale Kinetis"
	select ARCH_CORTEXM4
	select ARCH_HAVE_MPU
	select ARM_HAVE_MPU_UNIFIED
	select ARCH_HAVE_FPU
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_RAMFUNCS
	select ARCH_HAVE_I2CRESET
	---help---
		Freescale Kinetis Architectures (ARM Cortex-M4)

config ARCH_CHIP_KL
	bool "NXP/Freescale Kinetis L"
	select ARCH_CORTEXM0
	---help---
		Freescale Kinetis L Architectures (ARM Cortex-M0+)

config ARCH_CHIP_LC823450
	bool "ON Semiconductor LC823450"
	select ARCH_CORTEXM3
	select ARCH_HAVE_MPU
	select ARCH_HAVE_HEAPCHECK
	select ARCH_HAVE_MULTICPU
	select ARCH_HAVE_I2CRESET
	select ARCH_GLOBAL_IRQDISABLE
	---help---
		ON Semiconductor LC823450 architectures (ARM dual Cortex-M3)

config ARCH_CHIP_LM
	bool "TI/Luminary Stellaris"
	select ARCH_HAVE_MPU
	select ARM_HAVE_MPU_UNIFIED
	---help---
		TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)

config ARCH_CHIP_LPC11XX
	bool "NXP LPC11xx"
	select ARCH_CORTEXM0
	---help---
		NXP LPC11xx architectures (ARM Cortex-M0)

config ARCH_CHIP_LPC17XX
	bool "NXP LPC17xx"
	select ARCH_CORTEXM3
	select ARCH_HAVE_MPU
	select ARM_HAVE_MPU_UNIFIED
	select ARCH_HAVE_FETCHADD
	select ARMV7M_HAVE_STACKCHECK
	---help---
		NXP LPC17xx architectures (ARM Cortex-M3)

config ARCH_CHIP_LPC214X
	bool "NXP LPC214x"
	select ARCH_ARM7TDMI
	select ARCH_HAVE_LOWVECTORS
	---help---
		NXP LPC2145x architectures (ARM7TDMI)

config ARCH_CHIP_LPC2378
	bool "NXP LPC2378"
	select ARCH_ARM7TDMI
	select ARCH_HAVE_LOWVECTORS
	---help---
		NXP LPC2145x architectures (ARM7TDMI)

config ARCH_CHIP_LPC31XX
	bool "NXP LPC31XX"
	select ARCH_ARM926EJS
	select ARCH_HAVE_LOWVECTORS
	---help---
		NPX LPC31XX architectures (ARM926EJS).

config ARCH_CHIP_LPC43XX
	bool "NXP LPC43XX"
	select ARCH_CORTEXM4
	select ARCH_HAVE_MPU
	select ARM_HAVE_MPU_UNIFIED
	select ARCH_HAVE_FPU
	select ARCH_HAVE_FETCHADD
	---help---
		NPX LPC43XX architectures (ARM Cortex-M4).

config ARCH_CHIP_LPC54XX
	bool "NXP LPC54XX"
	select ARCH_CORTEXM4
	select ARCH_HAVE_MPU
	select ARM_HAVE_MPU_UNIFIED
	select ARCH_HAVE_FPU
	select ARCH_HAVE_FETCHADD
	---help---
		NPX LPC54XX architectures (ARM Cortex-M4).

config ARCH_CHIP_MOXART
	bool "MoxART"
	select ARCH_ARM7TDMI
	select ARCH_HAVE_RESET
	select ARCH_HAVE_SERIAL_TERMIOS
	---help---
		MoxART family

config ARCH_CHIP_NRF52
	bool "Nordic NRF52"
	select ARCH_CORTEXM4
	#select ARCH_HAVE_MPU
	#select ARM_HAVE_MPU_UNIFIED
	select ARCH_HAVE_FPU
	---help---
		Nordic NRF52 architectures (ARM Cortex-M4).

config ARCH_CHIP_NUC1XX
	bool "Nuvoton NUC100/120"
	select ARCH_CORTEXM0
	---help---
		Nuvoton NUC100/120 architectures (ARM Cortex-M0).

config ARCH_CHIP_SAMA5
	bool "Atmel SAMA5"
	select ARCH_CORTEXA5
	select ARCH_HAVE_FPU
	select ARCH_HAVE_IRQPRIO
	select ARCH_HAVE_LOWVECTORS
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_I2CRESET
	select ARCH_HAVE_TICKLESS
	select ARCH_HAVE_ADDRENV
	select ARCH_NEED_ADDRENV_MAPPING
	---help---
		Atmel SAMA5 (ARM Cortex-A5)

config ARCH_CHIP_SAMD2X
	bool "Atmel SAMD2x"
	select ARCH_CORTEXM0
	---help---
		Atmel SAMD (ARM Cortex-M0+)

config ARCH_CHIP_SAML2X
	bool "Atmel SAML2x"
	select ARCH_CORTEXM0
	---help---
		Atmel SAML (ARM Cortex-M0+)

config ARCH_CHIP_SAM34
	bool "Atmel SAM3/SAM4"
	select ARCH_HAVE_MPU
	select ARM_HAVE_MPU_UNIFIED
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_RAMFUNCS
	select ARMV7M_HAVE_STACKCHECK
	---help---
		Atmel SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures

config ARCH_CHIP_SAMV7
	bool "Atmel SAMV7"
	select ARCH_CORTEXM7
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_RAMFUNCS
	select ARCH_HAVE_TICKLESS
	select ARCH_HAVE_I2CRESET
	select ARCH_HAVE_SPI_CS_CONTROL
	select ARM_HAVE_MPU_UNIFIED
	select ARMV7M_HAVE_STACKCHECK
	---help---
		Atmel SAMV7 (ARM Cortex-M7) architectures

config ARCH_CHIP_STM32
	bool "STMicro STM32 F1/F2/F3/F4/L1"
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_I2CRESET
	select ARCH_HAVE_HEAPCHECK
	select ARCH_HAVE_PROGMEM
	select ARCH_HAVE_SPI_BITORDER
	select ARCH_HAVE_TICKLESS
	select ARCH_HAVE_TIMEKEEPING
	select ARM_HAVE_MPU_UNIFIED
	select ARMV7M_HAVE_STACKCHECK
	---help---
		STMicro STM32 architectures (ARM Cortex-M3/4).

config ARCH_CHIP_STM32F0
	bool "STMicro STM32 F0"
	select ARCH_CORTEXM0
	---help---
		STMicro STM32 architectures (ARM Cortex-M0).

config ARCH_CHIP_STM32F7
	bool "STMicro STM32 F7"
	select ARCH_CORTEXM7
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_I2CRESET
	select ARCH_HAVE_HEAPCHECK
	select ARCH_HAVE_SPI_BITORDER
	select ARM_HAVE_MPU_UNIFIED
	select ARMV7M_HAVE_STACKCHECK
	---help---
		STMicro STM32 architectures (ARM Cortex-M7).

config ARCH_CHIP_STM32H7
	bool "STMicro STM32 H7"
	select ARCH_CORTEXM7
	select ARCH_HAVE_MPU
#	select ARCH_HAVE_I2CRESET
#	select ARCH_HAVE_HEAPCHECK
	select ARCH_HAVE_SPI_BITORDER
	select ARM_HAVE_MPU_UNIFIED
#	select ARMV7M_HAVE_STACKCHECK
	---help---
		STMicro STM32H7 architectures (ARM Cortex-M7).

		BEWARE: This is a work-in-progress and not yet ready for general
		usage.  See configs/nucleo-h743zi/README.txt for the current state
		of the port.

config ARCH_CHIP_STM32L4
	bool "STMicro STM32 L4"
	select ARCH_CORTEXM4
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_I2CRESET
	select ARCH_HAVE_HEAPCHECK
	select ARCH_HAVE_PROGMEM
	select ARCH_HAVE_SPI_BITORDER
	select ARCH_HAVE_TICKLESS
	select ARM_HAVE_MPU_UNIFIED
	select ARMV7M_HAVE_STACKCHECK
	---help---
		STMicro STM32 architectures (ARM Cortex-M4).

config ARCH_CHIP_STR71X
	bool "STMicro STR71x"
	select ARCH_ARM7TDMI
	select ARCH_HAVE_LOWVECTORS
	---help---
		STMicro STR71x architectures (ARM7TDMI).

config ARCH_CHIP_TMS570
	bool "TI TMS570"
	select ENDIAN_BIG
	select ARCH_HAVE_LOWVECTORS
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_RAMFUNCS
	select ARMV7R_MEMINIT
	select ARMV7R_HAVE_DECODEFIQ
	---help---
		TI TMS570 family

config ARCH_CHIP_TIVA
	bool "TI Tiva"
	select ARCH_HAVE_MPU
	select ARM_HAVE_MPU_UNIFIED
	select ARCH_HAVE_FPU
	select ARCH_HAVE_FETCHADD
	---help---
		TI Tiva TM4C architectures (ARM Cortex-M4)

config ARCH_CHIP_XMC4
	bool "Infineon XMC4xxx"
	select ARCH_CORTEXM4
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FETCHADD
	select ARCH_HAVE_RAMFUNCS
	select ARCH_HAVE_I2CRESET
	select ARM_HAVE_MPU_UNIFIED
	select ARMV7M_HAVE_STACKCHECK
	---help---
		Infineon XMC4xxx(ARM Cortex-M4) architectures

endchoice

config ARCH_ARM7TDMI
	bool
	default n
	---help---
		The Arm7TDMI-S is an excellent workhorse processor capable of a wide
		array of applications. Traditionally used in mobile handsets, the
		processor is now broadly in many non-mobile applications.

config ARCH_ARM920T
	bool
	default n
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	---help---
		The ARM9 processor family is built around the ARM9TDMI processor and
		incorporates the 16-bit Thumb instruction set. The ARM9 Thumb family
		includes the ARM920T and ARM922T cached processor macrocells:

		- Dual 16k caches for applications running Symbian OS, Palm OS,
		  Linux and Windows CE,
		- Dual 8k caches for applications running Symbian OS, Palm OS, Linux
		  and Windows CE Applications

config ARCH_ARM926EJS
	bool
	default n
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	---help---
		Arm926EJ-S is the entry point processor capable of supporting full
		Operating Systems including Linux, WindowsCE, and Symbian.

		The ARM9E processor family enables single processor solutions for
		microcontroller, DSP and Java applications. The ARM9E family of
		products are DSP-enhanced 32-bit RISC processors, for applications
		requiring a mix of DSP and microcontroller performance. The family
		includes the ARM926EJ-S, ARM946E-S, ARM966E-S, and ARM968E-S
		processor macrocells. They include signal processing extensions to
		enhance 16-bit fixed point performance using a single-cycle 32 x 16
		multiply-accumulate (MAC) unit, and implement the 16-bit Thumb
		instruction set. The ARM926EJ-S processor also includes ARM Jazelle
		technology which enables the direct execution of Java bytecodes in
		hardware.

config ARCH_ARM1136J
	bool
	default n
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	---help---
		Arm1136J(F)-S is very similar to Arm926EJ-S, but includes an
		extended pipeline, basic SIMD (Single Instruction Multiple Data)
		instructions, and improved frequency and performance.

config ARCH_ARM1156T2
	bool
	default n
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	---help---
		Arm1156T2(F)-S is the highest-performance processor in the real-time
		Classic Arm family.

config ARCH_ARM1176JZ
	bool
	default n
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	---help---
		Arm1176JZ(F)-S is the highest-performance single-core processor in
		the Classic Arm family. It also introduced TrustZone technology to
		enable secure execution outside of the reach of malicious code.

config ARCH_CORTEXM0
	bool
	default n
	select ARCH_HAVE_IRQPRIO
	select ARCH_HAVE_RESET

config ARCH_CORTEXM23
	bool
	default n

config ARCH_CORTEXM3
	bool
	default n
	select ARCH_HAVE_IRQPRIO
	select ARCH_HAVE_RAMVECTORS
	select ARCH_HAVE_LAZYFPU
	select ARCH_HAVE_HIPRI_INTERRUPT
	select ARCH_HAVE_RESET

config ARCH_CORTEXM33
	bool
	default n

config ARCH_CORTEXM4
	bool
	default n
	select ARCH_HAVE_IRQPRIO
	select ARCH_HAVE_RAMVECTORS
	select ARCH_HAVE_LAZYFPU
	select ARCH_HAVE_HIPRI_INTERRUPT
	select ARCH_HAVE_RESET

config ARCH_CORTEXM7
	bool
	default n
	select ARCH_HAVE_FPU
	select ARCH_HAVE_IRQPRIO
	select ARCH_HAVE_RAMVECTORS
	select ARCH_HAVE_LAZYFPU
	select ARCH_HAVE_HIPRI_INTERRUPT
	select ARCH_HAVE_RESET
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXA5
	bool
	default n
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXA8
	bool
	default n
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXA9
	bool
	default n
	select ARCH_HAVE_MMU
	select ARCH_USE_MMU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXR4
	bool
	default n
	select ARCH_HAVE_MPU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXR4F
	bool
	default n
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FPU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXR5
	bool
	default n
	select ARCH_HAVE_MPU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXR5F
	bool
	default n
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FPU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXR7
	bool
	default n
	select ARCH_HAVE_MPU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_CORTEXR7F
	bool
	default n
	select ARCH_HAVE_MPU
	select ARCH_HAVE_FPU
	select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

config ARCH_FAMILY
	string
	default "arm"		if ARCH_ARM7TDMI || ARCH_ARM926EJS || ARCH_ARM920T
	default "armv6-m"	if ARCH_CORTEXM0
	default "armv7-a"	if ARCH_CORTEXA5 || ARCH_CORTEXA8 || ARCH_CORTEXA9
	default "armv7-m"	if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
	default "armv7-r"	if ARCH_CORTEXR4 || ARCH_CORTEXR4F || ARCH_CORTEXR5 || ARCH_CORTEXR5F || ARCH_CORTEX74 || ARCH_CORTEXR7F

config ARCH_CHIP
	string
	default "a1x"		if ARCH_CHIP_A1X
	default "bcm2708"	if ARCH_CHIP_BCM2708
	default "c5471"		if ARCH_CHIP_C5471
	default "dm320"		if ARCH_CHIP_DM320
	default "efm32"		if ARCH_CHIP_EFM32
	default "imx1"		if ARCH_CHIP_IMX1
	default "imx6"		if ARCH_CHIP_IMX6
	default "imxrt"		if ARCH_CHIP_IMXRT
	default "kinetis"	if ARCH_CHIP_KINETIS
	default "kl"		if ARCH_CHIP_KL
	default "lc823450"	if ARCH_CHIP_LC823450
	default "tiva"		if ARCH_CHIP_LM || ARCH_CHIP_TIVA
	default "lpc11xx"	if ARCH_CHIP_LPC11XX
	default "lpc17xx"	if ARCH_CHIP_LPC17XX
	default "lpc214x"	if ARCH_CHIP_LPC214X
	default "lpc2378"	if ARCH_CHIP_LPC2378
	default "lpc31xx"	if ARCH_CHIP_LPC31XX
	default "lpc43xx"	if ARCH_CHIP_LPC43XX
	default "lpc54xx"	if ARCH_CHIP_LPC54XX
	default "moxart"	if ARCH_CHIP_MOXART
	default "nrf52"		if ARCH_CHIP_NRF52
	default "nuc1xx"	if ARCH_CHIP_NUC1XX
	default "sama5"		if ARCH_CHIP_SAMA5
	default "samd2l2"	if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
	default "sam34"		if ARCH_CHIP_SAM34
	default "samv7"		if ARCH_CHIP_SAMV7
	default "stm32"		if ARCH_CHIP_STM32
	default "stm32f0"	if ARCH_CHIP_STM32F0
	default "stm32f7"	if ARCH_CHIP_STM32F7
	default "stm32h7"	if ARCH_CHIP_STM32H7
	default "stm32l4"	if ARCH_CHIP_STM32L4
	default "str71x"	if ARCH_CHIP_STR71X
	default "tms570"	if ARCH_CHIP_TMS570
	default "xmc4"		if ARCH_CHIP_XMC4

config ARMV7M_USEBASEPRI
	bool "Use BASEPRI Register"
	default n
	depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
	---help---
		Use the BASEPRI register to enable and disable interrupts. By
		default, the PRIMASK register is used for this purpose. This
		usually results in hardfaults when supervisor calls are made.
		Though, these hardfaults are properly handled by the RTOS, the
		hardfaults can confuse some debuggers. With the BASEPRI
		register, these hardfaults, will be avoided. For more details see
		http://www.nuttx.org/doku.php?id=wiki:nxinternal:svcall

config ARCH_HAVE_LAZYFPU
	bool

config ARMV7M_LAZYFPU
	bool "Lazy FPU storage"
	default n
	depends on ARCH_HAVE_LAZYFPU
	---help---
		There are two forms of the common vector logic.  There are pros and
		cons to each option:

		1) The standard common vector logic exploits features of the ARMv7-M
		   architecture to save the all of floating registers on entry into
		   each interrupt and then to restore the floating registers when
		   the interrupt returns.  The primary advantage to this approach is
		   that floating point operations are available in interrupt
		   handling logic.  Since the volatile registers are preserved,
		   operations on the floating point registers by interrupt handling
		   logic has no ill effect.  The downside is, of course, that more
		   stack operations are required on each interrupt to save and store
		   the floating point registers.  Because of the some special
		   features of the ARMv-M, this is not as much overhead as you might
		   expect, but overhead nonetheless.

		2) The lazy FPU common vector logic does not save or restore
		   floating point registers on entry and exit from the interrupt
		   handler. Rather, the floating point registers are not restored
		   until it is absolutely necessary to do so when a context switch
		   occurs and the interrupt handler will be returning to a different
		   floating point context.  Since floating point registers are not
		   protected, floating point operations must not be performed in
		   interrupt handling logic.  Better interrupt performance is be
		   expected, however.

		By default, the "standard" common vector logic is build.  This
		option selects the alternate lazy FPU common vector logic.

config ARCH_HAVE_FPU
	bool
	default n

config ARCH_HAVE_DPFPU
	bool
	default n

config ARCH_FPU
	bool "FPU support"
	default y
	depends on ARCH_HAVE_FPU
	---help---
		Build in support for the ARM Cortex-M4 Floating Point Unit (FPU).
		Check your chip specifications first; not all Cortex-M4 chips
		support the FPU.

config ARCH_DPFPU
	bool "Double precision FPU support"
	default y
	depends on ARCH_FPU && ARCH_HAVE_DPFPU
	---help---
		Enable toolchain support for double precision (64-bit) floating
		point if both the toolchain and the hardware support it.

config ARCH_HAVE_TRUSTZONE
	bool
	default n
	---help---
		Automatically selected to indicate that the ARM CPU supports
		TrustZone.

choice
	prompt "TrustZone Configuration"
	default ARCH_TRUSTZONE_SECURE
	depends on ARCH_HAVE_TRUSTZONE

config ARCH_TRUSTZONE_SECURE
	bool "All CPUs operate secure state"

config ARCH_TRUSTZONE_NONSECURE
	bool "All CPUs operate non-secure state"
	depends on EXPERIMENTAL

config ARCH_TRUSTZONE_BOTH
	bool "CPUs operate in both secure and non-secure states"
	depends on EXPERIMENTAL

endchoice # TrustZone Configuration

config ARM_HAVE_MPU_UNIFIED
	bool
	default n
	---help---
		Automatically selected to indicate that the CPU supports a
		unified MPU for both instruction and data addresses.

config ARM_MPU
	bool "MPU support"
	default n
	depends on ARCH_HAVE_MPU
	select ARCH_USE_MPU
	---help---
		Build in support for the ARM Cortex-M3/4/7 Memory Protection Unit (MPU).
		Check your chip specifications first; not all Cortex-M3/4/7 chips
		support the MPU.

config ARM_MPU_NREGIONS
	int "Number of MPU regions"
	default 16 if ARCH_CORTEXM7
	default 8 if !ARCH_CORTEXM7
	depends on ARM_MPU
	---help---
		This is the number of protection regions supported by the MPU.

config ARCH_HAVE_LOWVECTORS
	bool

config ARCH_LOWVECTORS
	bool "Vectors in low memory"
	default n
	depends on ARCH_HAVE_LOWVECTORS
	---help---
		Support ARM vectors in low memory.

config ARCH_ROMPGTABLE
	bool "ROM page table"
	default n
	depends on ARCH_USE_MMU
	---help---
		Support a fixed memory mapping use a (read-only) page table in ROM/FLASH.

config DEBUG_HARDFAULT
	bool "Verbose Hard-Fault Debug"
	default n
	depends on DEBUG_FEATURES && (ARCH_CORTEXM0 || ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
	---help---
		Enables verbose debug output when a hard fault is occurs.  This verbose
		output is sometimes helpful when debugging difficult hard fault problems,
		but may be more than you typically want to see.

config DEBUG_MEMFAULT
	bool "Verbose Mem-Fault Debug"
	default n
	depends on DEBUG_FEATURES && ARCH_USE_MPU
	---help---
		Enables verbose debug output when a mem fault is occurs.  This verbose
		output is sometimes helpful when debugging difficult mem fault problems,
		but may be more than you typically want to see.

if ARCH_CORTEXM0
source arch/arm/src/armv6-m/Kconfig
endif
if ARCH_CORTEXA5 || ARCH_CORTEXA8 || ARCH_CORTEXA9
source arch/arm/src/armv7-a/Kconfig
endif
if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
source arch/arm/src/armv7-m/Kconfig
endif
if ARCH_CORTEXR4 || ARCH_CORTEXR4F || ARCH_CORTEXR5 || ARCH_CORTEXR5F || ARCH_CORTEX74 || ARCH_CORTEXR7F
source arch/arm/src/armv7-r/Kconfig
endif
if ARCH_ARM7TDMI || ARCH_ARM920T || ARCH_ARM926EJS || ARCH_ARM1136J || ARCH_ARM1156T2 || ARCH_ARM1176JZ
source arch/arm/src/arm/Kconfig
endif
if ARCH_CHIP_A1X
source arch/arm/src/a1x/Kconfig
endif
if ARCH_CHIP_BCM2708
source arch/arm/src/bcm2708/Kconfig
endif
if ARCH_CHIP_C5471
source arch/arm/src/c5471/Kconfig
endif
if ARCH_CHIP_DM320
source arch/arm/src/dm320/Kconfig
endif
if ARCH_CHIP_EFM32
source arch/arm/src/efm32/Kconfig
endif
if ARCH_CHIP_IMX1
source arch/arm/src/imx1/Kconfig
endif
if ARCH_CHIP_IMX6
source arch/arm/src/imx6/Kconfig
endif
if ARCH_CHIP_IMXRT
source arch/arm/src/imxrt/Kconfig
endif
if ARCH_CHIP_KINETIS
source arch/arm/src/kinetis/Kconfig
endif
if ARCH_CHIP_KL
source arch/arm/src/kl/Kconfig
endif
if ARCH_CHIP_LC823450
source arch/arm/src/lc823450/Kconfig
endif
if ARCH_CHIP_LM || ARCH_CHIP_TIVA
source arch/arm/src/tiva/Kconfig
endif
if ARCH_CHIP_LPC11XX
source arch/arm/src/lpc11xx/Kconfig
endif
if ARCH_CHIP_LPC17XX
source arch/arm/src/lpc17xx/Kconfig
endif
if ARCH_CHIP_LPC214X
source arch/arm/src/lpc214x/Kconfig
endif
if ARCH_CHIP_LPC2378
source arch/arm/src/lpc2378/Kconfig
endif
if ARCH_CHIP_LPC31XX
source arch/arm/src/lpc31xx/Kconfig
endif
if ARCH_CHIP_LPC43XX
source arch/arm/src/lpc43xx/Kconfig
endif
if ARCH_CHIP_LPC54XX
source arch/arm/src/lpc54xx/Kconfig
endif
if ARCH_CHIP_MOXART
source arch/arm/src/moxart/Kconfig
endif
if ARCH_CHIP_NRF52
source arch/arm/src/nrf52/Kconfig
endif
if ARCH_CHIP_NUC1XX
source arch/arm/src/nuc1xx/Kconfig
endif
if ARCH_CHIP_SAMA5
source arch/arm/src/sama5/Kconfig
endif
if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
source arch/arm/src/samd2l2/Kconfig
endif
if ARCH_CHIP_SAM34
source arch/arm/src/sam34/Kconfig
endif
if ARCH_CHIP_SAMV7
source arch/arm/src/samv7/Kconfig
endif
if ARCH_CHIP_STM32
source arch/arm/src/stm32/Kconfig
endif
if ARCH_CHIP_STM32F0
source arch/arm/src/stm32f0/Kconfig
endif
if ARCH_CHIP_STM32F7
source arch/arm/src/stm32f7/Kconfig
endif
if ARCH_CHIP_STM32H7
source arch/arm/src/stm32h7/Kconfig
endif
if ARCH_CHIP_STM32L4
source arch/arm/src/stm32l4/Kconfig
endif
if ARCH_CHIP_STR71X
source arch/arm/src/str71x/Kconfig
endif
if ARCH_CHIP_TMS570
source arch/arm/src/tms570/Kconfig
endif
if ARCH_CHIP_XMC4
source arch/arm/src/xmc4/Kconfig
endif

endif # ARCH_ARM