Gregory Nutt
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df156de4a4
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Buildroot EABI (vs OABI) is now the default
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2014-02-28 07:49:15 -06:00 |
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Gregory Nutt
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764ba4da70
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SAMA5: Fix logic for running with data in SDRAM
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2014-01-29 07:49:23 -06:00 |
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Gregory Nutt
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3ddb0ebaef
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ARMv7-A: Conditionally compile out more unneeded logic when .data and .bss are in SDRAM
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2014-01-28 16:39:08 -06:00 |
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Gregory Nutt
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72ee80b7cc
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SAMA5: Mostly cosmetic
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2014-01-28 15:54:03 -06:00 |
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Gregory Nutt
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34b94de8fe
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Add support for .data and .bss in SDRAM
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2014-01-28 14:35:03 -06:00 |
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Gregory Nutt
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2f837ccd2a
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rename up_led*() functions to board_led_*()
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2014-01-24 14:28:49 -06:00 |
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Gregory Nutt
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f3f5378acc
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The optimization level can now be selected as part of the configuration
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2014-01-24 07:45:35 -06:00 |
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Gregory Nutt
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a6d486557b
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Cosmetic spaces to tabs change
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2013-12-08 10:38:33 -06:00 |
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Gregory Nutt
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126bec4e55
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Add more nops after enabling MMU for Cortex-A8
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2014-01-07 08:38:00 -06:00 |
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Gregory Nutt
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6a9c63aa09
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A10: Fix error in IRQ dispatch; vector table seems to be offset by 64 bytes?
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2013-12-07 08:36:30 -06:00 |
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Gregory Nutt
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bb92016356
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SVC is the preferred mnemonic vs. SWI for cortex A
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2014-01-05 16:21:41 -06:00 |
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Gregory Nutt
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88faa55ac1
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Fix some missing parameters in macros
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2013-12-22 16:29:36 -06:00 |
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Gregory Nutt
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ed56d3aa83
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Replace explicit hex MMU value with definition
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2013-12-18 12:47:43 -06:00 |
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Gregory Nutt
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e9d7ab1ba3
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A10: Extend register debug logic
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2013-12-18 11:26:48 -06:00 |
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Gregory Nutt
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e23dcc6384
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Cortex-A: Fix start-up cache invalidation logi
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2013-12-18 09:01:43 -06:00 |
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Gregory Nutt
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fa3593a2c5
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Remove executable mode bits
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2013-11-17 08:27:11 -06:00 |
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Gregory Nutt
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1771b69b62
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Cosmetic changes to comments and README files
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2013-12-16 13:48:20 -06:00 |
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Gregory Nutt
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cbe5751c3b
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Trivial updates to comments and README files
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2013-12-16 11:13:55 -06:00 |
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Gregory Nutt
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96918171ee
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Review Cortex-A9 CP15 registers and update register definitions
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2013-12-16 10:23:29 -06:00 |
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Gregory Nutt
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c4380b5a8f
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ARMv7-A: If the page table does not like in same address range as .text and primary RAM, then we will need to set up an additional mapping for the page table at boot time.
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2013-12-16 08:26:07 -06:00 |
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Gregory Nutt
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3f81d6f0b3
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Port IDLE/interrupt stack coloration to ARM and ARMv7-A architectures
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2013-11-01 15:30:18 -06:00 |
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Gregory Nutt
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f8b3dbaa61
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Extend stack debug logic to include IDLE and interrupt stacks. Also color the heap as well. Based on suggestions from David Sidrane
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2013-11-01 11:16:51 -06:00 |
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Gregory Nutt
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fa71c8211c
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SAMA5 LCDC: Correct how framebuffer memory was being mapped; Remove options to get framebuffer memory in various. Because of the mapping and aligment requirements, those options really cannot be supported
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2013-10-13 13:08:05 -06:00 |
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Gregory Nutt
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2de3781ebf
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Slightly improved debug output
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2013-09-24 13:47:03 -06:00 |
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Gregory Nutt
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8a1e33cb10
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Un-neccesary, cosmetic changes to label names and comments
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2013-09-22 08:54:06 -06:00 |
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Gregory Nutt
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9cb23c5ccb
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ARMv7-A: Fix some error in alignment to cache line boundaries in the cache operations
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2013-09-21 15:47:00 -06:00 |
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Gregory Nutt
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c900c580ae
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ARMv7-A: Clarify end address paramet in cache operations: It is the end+1 address, not the end address
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2013-09-21 12:16:34 -06:00 |
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Gregory Nutt
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bc46b447dc
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Fix all occurrences of "the the" in documentation and comments
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2013-08-27 09:40:19 -06:00 |
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Gregory Nutt
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2feb83a2f8
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SAMA5: More MMU-related changes to properly initialize SDRAM
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2013-08-02 11:11:57 -06:00 |
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Gregory Nutt
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b148465beb
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ARMv7-A: Map all of .text, .bss, .data., stacks before enabling the MMU and caching. This is simpler and avoids fears I have about caching
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2013-08-01 10:05:33 -06:00 |
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Gregory Nutt
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f2195a16b2
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ARMv7-A: Separate CONFIG_PAGING start-up logic into a different startup file. Too much conditional compilation.
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2013-08-01 07:41:00 -06:00 |
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Gregory Nutt
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fde3777e9e
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Fix Cortex-A CPSR register field definition
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2013-07-30 19:05:24 -06:00 |
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Gregory Nutt
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8bfdf70766
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ARMv7-A: Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM
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2013-07-30 13:20:33 -06:00 |
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Gregory Nutt
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413aba0bf5
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SAMA5: More cache and mmu inline utility functions
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2013-07-29 19:57:15 -06:00 |
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Gregory Nutt
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36b1cd0a6b
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SAMA5: Separate cache operations into separate files
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2013-07-29 18:38:02 -06:00 |
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Gregory Nutt
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5351598323
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Changes to ARMv7-A boot logic to handle the case where we execute out of NOR FLASH
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2013-07-29 17:54:56 -06:00 |
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Gregory Nutt
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4ba648aaae
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SAMA5: Add file structure to support board-specific initialization of NOR flash
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2013-07-29 07:41:53 -06:00 |
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Gregory Nutt
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9a94a3707c
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SAMA5: The ostest configuration have been converted to run out of NOR flash. There is more to be done, however
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2013-07-28 15:07:35 -06:00 |
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Gregory Nutt
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7dc8dd4b50
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SAMA5: Correct a clock configuration bug; clarify some MMU memory types
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2013-07-28 12:44:06 -06:00 |
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Gregory Nutt
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263678e05b
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SAMA5: Correct vector mapping
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2013-07-28 09:44:11 -06:00 |
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Gregory Nutt
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f0e3011fc3
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Removed unused ARMv7-A cache function
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2013-07-27 14:03:02 -06:00 |
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Gregory Nutt
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efa21b82bc
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SAMA5: Fix heap allocation bugs
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2013-07-27 11:28:31 -06:00 |
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Gregory Nutt
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c4ec723089
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SAMA5 page table is cached; need to flush the cache each time that the page table is updated
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2013-07-27 09:27:37 -06:00 |
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Gregory Nutt
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6fc4b9aacc
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Correct an error in Cortex-A5 intermediate MMU mapping
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2013-07-26 17:26:53 -06:00 |
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Gregory Nutt
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dc92037e67
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Add a hello world configuration to help with the SAMA5 bringup
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2013-07-26 15:28:01 -06:00 |
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Gregory Nutt
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70f0ffdfc5
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Finally... renamed all CONFIG_DRAM_ settings to CONFIG_RAM_
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2013-07-26 10:09:17 -06:00 |
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Gregory Nutt
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ec8a56259c
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SAMA5: If the page table is in high memory, make sure that it is excluded from the heap
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2013-07-26 09:16:46 -06:00 |
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Gregory Nutt
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49f9b7040e
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Misc Cortex-A5 MMU-related fix -- still does not boot
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2013-07-25 16:37:55 -06:00 |
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Gregory Nutt
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55df28dbcf
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Fix an uninitialized register error that crept into the ARM9 start up code many years ago and was recently cloned into the Cortex-A5. Obviously no on has used NuttX with ARM9 for years
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2013-07-24 20:12:04 -06:00 |
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Gregory Nutt
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e6beda428a
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Fix SAMA5 vector linking issue
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2013-07-24 12:51:42 -06:00 |
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